Specifications

Table Of Contents
Cinterion
®
TX62-W/TX82-W Hardware Interface Description
1.4 Circuit Concept
21
t TX62-W_TX62-W-x_TX82-W-x_HID_v01.200d 2022-09-08
Public / Preliminary
Page 19 of 170
Figure 4: TX62-W block diagram
19.2MHz
32.768kHz
19.2MHz
with
Temp.Sensor
X-tal:
Control interface
Reset
HWID’s
GPIO’s
GNSS
LTE
Antenna LGA Pads
LGA Pads
GSM/CatM1/CatNB
Baseband controller
with integrated memory
ADC
RF
Interrupt
BATT+_RF
RF Transceiver
LTE PA+ASM
3
4
Power Management
IC
Power Supply
Power Supply
Serial (ASC0)
Serial (ASC1/GPIO)
USB 2.0
USIM
CCIN
FST_SHDN
STATUS (GPIO)
SUSPEND_MON
SIM_SWITCH (GPIO)
GPIO (not shared)
I
2
C
SPI (GPIO)
VUSIM
ADC1
EMERG_RST
ON
V180
VCORE
BATT+
RF
BATT+
BB
eUICC (optional)
8
I/Q-signals
(2x2)
SDR_ASM_ANT
RF_CLK1
SDR_GNSS
BATT+
PS_HOLD
REFE 1...2_
CLK_DATA
4
GPDATA
STMR_SYNC
BATT +
IN
EN
OUT
LDO
USB_VDDA
_3P3
GPIO
RF Part
eUICC
(MFF-XS eUICC)
5
Coupler
TX_PA1(LTE_LB)
Matching
GN SS
SAW filter
B71_RX
LB LPF
3
6
4
2