Specifications

Cinterion
®
TX62-W/TX82-W Hardware Interface Description
1.4 Circuit Concept
21
t TX62-W_TX62-W-x_TX82-W-x_HID_v01.200d 2022-09-08
Public / Preliminary
Page 21 of 170
Figure 6: TX62-W-C block diagram
Please note that the I
2
C function and some GPIO lines are available with the embedded pro-
cessing option only. Also, some GPIO lines may be shared with further functions that are also
only available with the embedded processing option. For details see Section 2.1, and Section
2.1.8.1.
19.2MHz
32. 768kHz
19.2MHz
with
Temp.Sensor
X-tal:
Control interface
Reset
HWID s
GPIO s
GNSS
LTE
Antenna LGA Pads
LGA Pads
GSM/CatM1/CatNB
Baseband Controller
With Integrated Memory
ADC
RF
Interrupt
BATT+_RF
RF
Transceiver
BATT_RF
3
4
Power
Management
IC
Power Supply
Power Supply
ASC0
ASC1
USB 2.0
USIM
CCIN
FAST_SHDN
STATUS (GPIO)
SUSPEND_MON
SIM_SWITCH (GPIO)
GPIO (not shared)
I
2
C
SPI (GPIO)
VUSIM
ADC1
EMERG_RST
ON
V180
VCORE
BATT+RF
BATT+BB
eUICC (optional)
8
I/Q-signals
(2x2)
RX_LTE
RF_CLK1
GNSS
2
LTE PC3 PA
+ASM
BATT+
PS_HOLD
2
REFE 1...2_
CLK_ DATA
4
GPDATA
STMR_SYNC
BATT+
IN
EN
OUT
LDO
USB_VDDA
_3P3
GPIO
REFE 2 _CLK_DATA
2
RF Part
5
TX_LB_LTE
TX_MB_LTE
GNSS
SAW filter
B31/72_RX
B31/72_DA_OUT
LB LP F
B31/72 PA
B31/ 72 filter
HDET
2
PA_CTRL
7
4
eUICC
(MFF-XS eUICC)