Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.2 RF Antenna Interface
- 2.3 GNSS Interface
- 2.4 Sample Application
- 3 Operating Characteristics
- 3.1 Operating Modes
- 3.2 Power Up/Power Down Scenarios
- 3.3 Power Saving
- 3.4 Power Supply
- 3.5 Operating Temperatures
- 3.6 Electrostatic Discharge
- 3.7 Blocking against RF on Interface Lines
- 3.8 Reliability Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 4.1 Mechanical Dimensions of TX62-W
- 4.2 Mechanical Dimensions of TX82-W, TX82-W-B, TX62-W-B and TX62-W-C
- 4.3 Mounting TX62/TX82 onto the Application Platform
- 4.4 Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
Cinterion
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TX62-W/TX82-W Hardware Interface Description
2.1 Application Interface
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t TX62-W_TX62-W-x_TX82-W-x_HID_v01.200d 2022-09-08
Public / Preliminary
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2.1.4 Serial Interface ASC0
TX62/TX82 offers an 8-wire unbalanced, asynchronous modem interface ASC0 conforming to
ITU-T V.24 protocol DCE signaling. The electrical characteristics do not comply with ITU-T
V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit
or inactive state). For electrical characteristics please refer to Table 4. For an illustration of the
interface line’s startup behavior see Figure 11.
TX62/TX82 is designed for use as a DCE. Based on the conventions for DCE-DTE connections
it communicates with the customer application (DTE) using the following signals:
• Port TXD @ application sends data to the module’s TXD0 signal line
• Port RXD @ application receives data from the module’s RXD0 signal line
Figure 10: Serial interface ASC0
Features:
• Includes the data lines TXD0 and RXD0, the status lines RTS0 and CTS0 and, in addition,
the modem control lines DTR0, DSR0, DCD0 and RING0.
• The RING0 signal serves to indicate incoming calls and other types of URCs (Unsolicited
Result Code). It can also be used to send pulses to the host application, for example to
wake up the application from power saving state.
• By default configured to 8 data bits, no parity and 1 stop bit.
• ASC0 can be operated at fixed bit rates from 300bps up to 921,600bps.
• Supports RTS0/CTS0 hardware flow control as a configuration option (see [1]). The hard-
ware hand shake line RTS0 has an internal pull down resistor causing a low level signal, if
the line is not used and open. Although hardware flow control is recommended, this allows
communication by using only RXD and TXD lines.
• Wake up from SLEEP mode by RTS0 activation (high to low transition; see Section 3.3.1.1).