Specifications

Table Of Contents
Cinterion
®
TX62-W/TX82-W Hardware Interface Description
2.1 Application Interface
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2.1.8 GPIO
TX82-W, TX82-W-B, TX62-W-B and TX62-W-C have 7 GPIOs (GPIO6-7,20-23,25) and TX62-
W has 6 GPIOs (GPIO7,20-23,25) for external hardware devices. Each GPIO can be config-
ured for use as input or output. All settings are AT command controlled. The configuration is
non-volatile and available after module restart.
The IO port driver has to be opened before using and configuring GPIOs. Before changing the
configuration of a GPIO pin (e.g. input to output) the pin has to be closed. If the GPIO pins are
not configured or the pins/driver were closed, the GPIO pins are high-Z with pull down resistor.
If a GPIO is configured to input, the pin has high-Z without pull resistor.
The following figure shows the start up behavior of the GPIOs interface.
Figure 19: GPIO start up behavior
With the embedded processing option of TX62/TX82 additional GPIOs are provided and can
be used - see below Section 2.1.8.1.
EMERG_RST
V180
GPIO6,7,20-23,25
Reset State
PD
Start up
Power supply active
Firmware
Initialization
Command Interface
Initialization
CTS0
ON
VCORE
High-Z/PD