Specifications

Cinterion
®
TX62-W/TX82-W Hardware Interface Description
3.2 Power Up/Power Down Scenarios
120
t TX62-W_TX62-W-x_TX82-W-x_HID_v01.200d 2022-09-08
Public / Preliminary
Page 81 of 170
3.2.3 Signal States after Startup
Table 18 describes various states interface signals pass through after startup until the system
is active.
Signals are in an initial state while the module is initializing. Once the startup initialization has
completed, i.e. when the software is running, all signals are in a defined state, the module is
ready to receive and transmit data. The state of some signals may change again once a re-
spective interface is activated or configured by AT command. For details on certain other signal
state changes during startup see also Section 3.2.1 (ON, VCORE, V180), Section 3.2.2
(EMERG_RST), and Section 2.1.4 (ASC0 signals).
Abbreviations used in above Table 18:
Table 18: Signal states
Signal name Reset state First start up configuration
CCIO PD O / L
CCRST PD O / L
CCCLK PD O / L
CCIN PD I / PD
RXD0 PD O / H
TXD0 PD I / PD
CTS0 PD O / H
RTS0 PD I / PD
DTR0 PD I / PU
DCD0 PD O / H
DSR0 PD O / H
RING0 PD O / H
RXD1 PD O / H
TXD1 PD I / PD
CTS1 PD O / H
RTS1 PD I / PD
STATUS PD I / PD
FST_SHDN PD I / PU
I2CDAT
1
1. Available with embedded processing option only.
PD OD
I2CCLK
1
PD OD
SIM_SWITCH PD I / PD
SUSPEND_MON PD I / PD
GPIO6,7,20-23,25 PD High-Z / PD
L = Low level
H = High level
High-Z = High Impedance
I = Input
O = Output
OD = Open Drain
PD = Pull down, 55kΩ ~390kΩ
PU = Pull up, 55kΩ ~390kΩ