AN364 Application Note Design Guide for a CS1610 and CS1611 Dimmer-Compatible SSL Circuit 1 Overview of the CS1610/11 The CS1610 and CS1611 are digital control ICs engineered to deliver a high-efficiency, cost-effective, flicker-free, phase-dimmable, solid-state lighting (SSL) solution for the incandescent lamp replacement market. The CS1610/11 is designed to control a quasi-resonant flyback topology. The CS1610 and CS1611 are designed for 120VAC and 230VAC line voltage applications, respectively.
AN364 IMPORTANT SAFETY INSTRUCTIONS Read and follow all safety instructions prior to using this demonstration board. This Engineering Evaluation Unit or Demonstration Board must only be used for assessing IC performance in a laboratory setting. This product is not intended for any other use or incorporation into products for sale. This product must only be used by qualified technicians or professionals who are trained in the safety procedures associated with the use of demonstration boards.
AN364 2 Introduction This application note is a guide to designing a Solid State Lighting (SSL) LED lamp circuit using Cirrus Logic's CS1610/11. The first half of the document presents a step-by-step design procedure for calculating the required components for each stage of the system. The second half of the document supports the design effort by showing an example of a CS1611 design. The CS1611 example will be based on the Cirrus Logic CRD1611-8W reference design.
AN364 3 Design Process The design process for a two-stage power converter system can be partitioned into six circuit blocks (see Figure 1). The AC line voltage is passed through an electromagnetic interference (EMI) filter to suppress conducted interference found on the power line. The output of the EMI filter is then converted to the desired DC output by a boostflyback converter. The power converter system includes the Gate Bias, Steady State Supply, and Active Clamp support circuitry.
AN364 3.2 Overview of Design Steps The CS1610/11 LED driver IC controls a power converter system that has two distinct power conversion stages. The IC requires supporting circuitry to provide a steady state power supply with gate bias, a clamp circuit, and EMI filtering. The recommended design process is outlined below: 1. Start with the flyback stage. 2. Design for full power at minimum VBST. Note that any design may require design trade-offs for different operating parameters. 3.
AN364 3.3 Flyback Stage Design Figure 2 illustrates the steps for designing the flyback stage. Flyback Specification Steps for the Flyback Design Determine N, Fsw, V Reflected, and VCLAMP 1. Set boost output voltage VBST . 2. Select a MOSFET that aligns with the quality standards of the designer’s company. 3. Determine the transformer turns ratio from the VBST, FET voltage, and reflected voltage VReflected. Estimate T3 Calculate TTfb 4.
AN364 Step 1) Select a Value for Boost Output Voltage The value of the boost output voltage, VBST, must be greater than the maximum input AC line voltage peak. The maximum VBST voltage, VBST(max), should be kept as low as possible to help maintain the FET breakdown requirement within economical constraints. VBST is determined by an internal parameter and changes slightly depending on the type of dimmer detected. With sense resistors R7, R8, R14, and R15 set to 1.
AN364 For optimum efficiency, the increase in transformer losses (created by an uneven duty cycle) must balance the reduction of the losses caused by discharging the leakage inductance (obtained by increasing the overshoot voltage). Equation 3 is used to balance all voltages contributing to the FET voltage drain and source. V Breakdown = V BST + V Reflected + V CLAMP – V Reflected + V M arg in [Eq.
AN364 Figure 4 illustrates the switching frequency used in the system design. i(t) Peak Primary Current, IPK( FB) Secondary Current Primary Current No Current T1 T2 T3 t TT Figure 4. Timing Diagram of T1, T2, T3, and TT Solve for T1 and T2 using Equation 7 and Equation 8: V Reflected 1 T1 = --------- – T3 --------------------------------------------------- V Reflected + V BST F sw [Eq.
AN364 Step 9) Calculate RFBGAIN (R17) Use Equation 12 to calculate the flyback gain resistor, RFBGAIN (R17). 4M R FBGAIN = ---------------------------------------------TT fb ---------- T2 fb 128 – 64 [Eq. 12] where R17 = RFBGAIN in TTfb = switching period TT at full brightness (full load condition) T2fb = period T2 at full brightness (full load condition) Step 10) Determine the RMS Current in the Winding Determining RMS current IRMS is necessary to properly define the wire size.
AN364 Step 13) Circuit Adjustments Circuit adjustments are required after the transformer has been designed and constructed. Recalculate RFBGAIN using Equation 12. Flyback gain FBGain is an internal constant that is programmable by RFBGAIN. TT fb FB Gain = ----------T2 fb [Eq. 16] FBGain is used in the flyback algorithm to control switching period TT. The range of FBGain is limited to: 1 FB Gain 2.5 [Eq. 17] T2 fb TT fb 2.5 T 2 fb 0 V Reflected 1.5 V BST 15.
AN364 Notes on Circuit Fine Tuning • Going beyond the RFBGAIN limitation will not have any further effect on the design. • RSense and RFBGAIN are frequently adjusted simultaneously to reach the desired operating point. • The optimized final design will have a slightly different switching frequency variation than the first design iteration. • When the load is increased or decreased by 10%, then RSense needs to be decreased or increased by less than 10%, respectively.
AN364 Step 15) Determine IPK(BST), ISAT, and RIPK (R13) The boost stage peak current has two distinct values: • IPK(BST) is related to input power PIN. The boost inductor current reaches this value during a substantial portion of the line-cycle, affecting the RMS value of the inductor and line current. • ISAT is a constant value of 0.6A and is independent of the power level. ISAT is necessary to maintain the dimmer TRIAC in the conduction mode.
AN364 The AC line current does not follow the inductor peak current envelope because the circuit operates in CRM and DCM. The switching frequency and duty cycle changes across the AC line phase resulting in a changing average value after the EMI filter smoothing. 0.14 AC Line Current Inductor Peak Current 0.12 0.10 Current (A) 0.08 0.06 0.04 0.02 0.00 0 15 30 45 60 75 90 105 120 135 150 165 180 Phase Angle (°) Figure 7.
AN364 The frequency range should be as high as possible without exceeding 75kHz. This strategy will keep the fundamental and second harmonic below the 150kHz EMI requirements. 140 120V Min Freq 130 120V Max Freq Switching Frequency (kHz) 120 230V Min Freq 110 230V Max Freq 100 90 80 70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 Power Multiplied by Inductance (Watts Multiplied by mH) 120 130 140 Figure 8.
AN364 Step 18) Determine Boost Input Capacitor To be compatible with a wide range of dimmers, the boost input capacitance should be minimized. Large input capacitance impacts the ability of the controller to properly sustain the current required by the dimmer and may cause oscillation. Capacitors should not be connected to the AC line side of the bridge rectifier. Added AC lineside capacitance alters the dimmer behavior in multi-lamp configurations and shifts the dimming curve.
AN364 The BSTAUX pin and FBAUX pin currents must be limited to less than 1mA. A series resistor of at least 22 k must be used to limit the current. Step 22) Overvoltage Protection Output open circuit protection and output overvoltage protection (OVP) are implemented by monitoring the output voltage through the flyback transformer auxiliary winding.
AN364 Solving Equation 25 for ‘CODE’: N 2 V CONNECT th CODE = ------------------------------------------------------------------I CONNECT R NTC + R S 256 1.25 V = ---------------------------------------------------------- 80A R NTC + R S [Eq. 26] 4M = -------------------------------- R NTC + R S The tracking range of this resistance ADC is approximately 15.5k to 4M.
AN364 excess charge from capacitor C4 by turning ‘ON’ transistor Q3, dissipating the power into load resistors R6 and R16. The clamp load resistors R6 and R16 must each be 2k 2W resistors for 230V and 500 2W resistors for 120V systems. Step 25) Designing the EMI Filter The switching frequency of the CS1610/11 can cause resonance in the EMI filter, so it is important to carefully design it. Resonance can cause undue noise, oscillation, and impact power factor.
AN364 4 Design Example The Cirrus Logic CRD1611-8W reference design is used for the design example. The required operating parameters for the analytical process are outlined in the table below. Parameters Output Power Symbol Value POUT 6.6W VIN 230V Output Voltage VOUT 15V Load Current IOUT 440mA Fsw(max) 85kHz AC Line Input Voltage Maximum Switching Frequency* * Increasing Fsw reduces the size of the magnetics but increases switching losses in the FET. 4.
AN364 Step 5) Determine the Flyback Nominal Timing T1 and T2 Use Equation 7 to solve for T1: V Reflected 1 220V 1 T1 = --------- – T3 ---------------------------------------------------- = ------------------ – 1s ----------------------------------- = 4.14s V Reflected + V BST 85kHz 220V + 405V F sw [Eq. 31] Use Equation 8 to solve for T2: V BST 1 405V 1 T2 = --------- – T3 ---------------------------------------------------- = ------------------ – 1s ----------------------------------- = 7.
AN364 Using Equation 13, calculate the transformer T1 secondary RMS current: I RMS = I PK FB N T current -------------------- = 0.131A 14.3 3 TT 7.45s --------------------------3 12.5s [Eq. 38] = 850mA Step 11) Determine Output Capacitor Output capacitor C5 ripple current IRipple(RMS) is the vectorial difference between transformer T1 secondary current and the DC load current. See Equation 39. I Ripple RMS = 2 2 [Eq. 39] 0.85A – 0.44A = 0.
AN364 Using Equation 20, calculate RIPK: 3 3 15.625 10 V 15.625 10 V R IPK = ------------------------------------------- = ------------------------------------------- = 134k I PK BST 116mA [Eq. 41] Step 16) Boost Inductor Specifications See Figure 8 in the Boost Inductor Specifications section on page 11. Choosing a maximum switching frequency of 110kHz, find the intersection with the 230V maximum switching curve, and get the corresponding power.
AN364 4.3 Final Design Steps Step 19) Choose Power Components The drain current through transistor Q4 is limited to 165mA. The smallest 800V MOSFET in a package capable of handling the power is 1A. The flyback stage output diode D3 has a peak current of 14.3 0.131 = 1.87A, an average DC current of 0.44A, and a maximum reverse voltage of 445/14.3 + 15 = 46V. A 1A 60V Schottky diode meet the requirements. The boost diode D1 has a peak current of 0.6A and an average DC current of 7.3W/405V = 18mA.
ECO 4.7K 915 L1 4.7mH + 1 E1 F1 1A 4 BR1 HD04-T 3 LINE - C1 1 2 4 5 C4 ELEC 4.7uF A3 CHANGED U1 PIN 6 & 7 PINNAMES TO NC 2200pF T1 RM06-CL01 3 A7 4 22.1K 04/30/12 D3 2 E3 1 LED+ SS26-TP C5 ELEC 100uF R5 27K 1% E4 B8 LED- 1 D2 STTH1L06A 12/22/11 1/6/12 CHANGED C5 TO EL LO ESR Z2 P6KE350A 300V 1 R11 2 2 L2 4.7mH Q3 FQN1N50CTA R3 4.7K R10 22 OHM R7 1.50M R14 1.50M C9 X7R 0.33uF C2 0.1UF D5 BAV23S-7-F R8 1.50M 2W 2K R4 R22 69.8K R15 1.
6 BOARD LAYOUT 1 1 2 1 2 2 1 2 2 2 1 8 4 4 5 1 1 2 3 2 7 1 1 2 2 1 1 2 2 3 2 1 2 1 1 2 1 Figure 12.
AN364REV3 7 Bill of Materials CIRRUS LOGIC CRD1611-8W_Rev_A.
AN364 Revision History 28 Revision Date Changes REV1 MAR 2012 Initial release REV2 JUNE 2012 Corrected typographical errors. REV3 AUG 2012 Context change and corrected typographical errors.
