User guide

AN375
AN375REV4 11
allow the RC circuit to respond to the variable dissipation requirements. The RC circuit should be designed to
track voltage V
rect
.
There are many variables associated with the RC snubber circuit design. Many of the variables are not well
controlled, therefore the best approach is to start with a conservative value for the RC snubber resistor and
increase its value while monitoring the power FET drain voltage at the peak of the line voltage until the highest
safe drain voltage is reached. The RC snubber resistor R
Snubber
dissipation at the line peak is defined by
Equation 9:
Increasing resistor R
Snubber
causes clamp voltage V
RC
to rise but not as much as to keep the power constant,
suggesting that there is an advantage to use as high a snubber resistor R
Snubber
as possible.
Step 3) Determine the Flyback Transformer Turns Ratio
Select a turns ratio N based on the output voltage V
OUT
and reflected voltage V
Reflected
using Equation 10:
where
V
OUT(max)
= the maximum LED string forward voltage V
OUT
at full current plus the rectifying diode voltage V
F
Step 4) Predicting T3
The time interval T3
PFC(90°)
is one-half the transformer self-resonance period when in PFC mode. A starting
value for T3
PFC(90°)
, as measured in typical designs, ranges between 1µs and 2µs and tends to be on the
lower side as power rises.
The resonant frequency is defined by the primary winding magnetizing inductance and the parasitic
capacitance at the drain of the power FET Q4, which includes the parasitic capacitance across the flyback
transformer primary winding, the FET Q4 drain to source, and the reflected capacitance due to the rectifier
diode D7. At the line peak in PFC mode (No-dimmer Mode) the flyback operates in quasi resonant mode. Time
T3
PFC(90°)
is close to one-half of the transformer in-circuit resonant period.
where
L
P
= flyback transformer primary inductance
C
P
= total parasitic capacitance at the drain of the power FET Q4
Step 5) Calculate Duty Cycle in Dimmer Mode
Since period T3 is not calculated but measured, the design process must account for it at the start of the
design. Duty cycle
, which is based on periods T3 and TT, is calculated using peak line voltage V
INPK
and
reflected voltage V
Reflected
. See Equation 13:
When determining peak current I
PK
in the primary-side FET, use Equation 13 with values that render a
minimum duty cycle

min
.
P
leakage
V
RC
2
R
Snubber
------------------------
=
[Eq. 9]
N
N
P
N
S
-------
V
Reflected
V
OUT max
----------------------------==
[Eq. 10]
TT
PFC 90
1
F
SW 90
-----------------------
=
[Eq. 11]
T3
PFC 90
 L
P
C
P
=
[Eq. 12]

1
T3
TT
-------
–


1
V
INPK
V
Reflected
--------------------------
+


--------------------------------------------
=
[Eq. 13]