Manual

ManualsBrandsCirrus Logic ManualsHardwareCDB4353

http://www.cirrus.com

Evaluation Board for the CS4353

Features

 Demonstrates Recommended Layout and

Grounding Arrangements

 CS8416 Receives S/PDIF, & EIAJ-340-

Compatible Digital Audio

 Headers for External PCM Audio

 Single-ended Stereo Analog Outputs

 Requires Only a Digital Signal Source and a

+3.3 V Power Supply for a Complete Digital-to-

Analog Converter System

 Configured by On-board Hardware Controls

 Power, Digital Source Select, and S/PDIF Error

Indicator LEDs

 Current Sense Resistors for CS4353 Supplies

(VA, VL, and VCP)

Description

The CDB4353 evaluation board is an excellent means

for quickly evaluating the CS4353 24-bit, high-perfor-

mance stereo D/A converter. Evaluation requires an

analog signal analyzer, a digital signal source, and a

+3.3 V power supply. Analog line-level outputs are pro-

vided via RCA phono jacks.

The CS8416 digital audio receiver IC provides the sys-

tem timing necessary to operate the Digital-to-Analog

converter and will accept S/PDIF and EIAJ-340-com-

patible audio data. The evaluation board may also be

configured to accept external timing and data signals for

operation in a user application during system

development.

The CDB4353 is controlled by switches to select the

digital signal source and configuration options for the

CS4353. Current sense resistors allow for easy power

calculations during system development.

ORDERING INFORMATION

CDB4353 Evaluation Board

Indicator LEDs

S/PDIF Error

S/PDIF or PCM Input Selected

+3.3V power

VL power

CS4353

CS8416

S/PDIF

Receiver

PCM Mux

and Level

Shifter

PCM Clocks/Data

CS4353 Settings

PCM source select

CS8416 serial port

format

Analog Outputs

Hardware Control

Switches

Reset Circuit

CS4353 Reset

CS8416 Reset

External

System

Connector

PCM Clocks/DataPCM Clocks/Data

PCM Input

Optical

S/PDIF

Input

AOUTA

AOUTB

PCM Header

Coaxial

S/PDIF

Input

+3.3V Power

(Optional separate VL)

AUG '08

DS803DB2

CDB4353

Summary of content (18 pages)

PAGE 1
CDB4353 Evaluation Board for the CS4353 Features Description Demonstrates Recommended Layout and The CDB4353 evaluation board is an excellent means for quickly evaluating the CS4353 24-bit, high-performance stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, and a +3.3 V power supply. Analog line-level outputs are provided via RCA phono jacks.
PAGE 2
CDB4353 TABLE OF CONTENTS 1. CDB4353 SYSTEM OVERVIEW ............................................................................................................ 4 2. CS4353 DIGITAL-TO-ANALOG CONVERTER ..................................................................................... 4 3. CS8416 DIGITAL AUDIO RECEIVER .................................................................................................... 4 4. INPUT FOR CLOCKS AND DATA .........................................................
PAGE 3
CDB4353 LIST OF TABLES Table 1. Switch S1 Quick Setup .................................................................................................................. 5 Table 2. System Connections .................................................................................................................... 6 Table 3. CDB4353 Jumper Settings ............................................................................................................ 6 Table 4. CDB4353 Switch Settings .................
PAGE 4
CDB4353 1. CDB4353 SYSTEM OVERVIEW The CDB4353 evaluation board is an excellent means of quickly evaluating the CS4353. The CS8416 digital audio interface receiver provides an easy interface to digital audio signal sources, including the majority of digital audio test equipment. The evaluation board also allows the user to supply external PCM clocks and data through two separate header options for system development. Configuration of the CDB4353 can be modified through piano switch S1, see Table 4.
PAGE 5
CDB4353 5. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by two binding posts, GND and +3.3 V (see Figure 33). The allowable input voltage range for the binding posts is 3.13 V to 3.47 V. The VL supply can be connected to the +3.3 V binding post by shunting J1 or provided externally by removing the shunt on J1 and connecting another voltage to pin 2 of J1 (labeled VL). VCP and VA are normally supplied by the 3.
PAGE 6
CDB4353 10.BOARD CONNECTIONS AND SETTINGS Board connections and settings are shown in Table 2, Table 3, and Table 4 below. CONNECTOR INPUT/OUTPUT 3.3 V - J3 Input SIGNAL PRESENT +3.
PAGE 7
CDB4353 11.PERFORMANCE PLOTS Test conditions (unless otherwise specified): TA = 25°C; VCP = VA = VL = 3.3 V; AGND = DGND =CPGND = 0 V; OPT1 S/PDIF input source; PCM data Left-Justified format; 2 VRMS output; De-emphasis off; input test signal is a 997 Hz sine wave at 0 dBFS; dB values relative to 2.1 VRMS full-scale output; measurement bandwidth 10 Hz to 20 kHz. CDB4353 revision A3 with CS4353 revision B1 used.
PAGE 8
CDB4353 +5 +40 +35 +4 +30 +25 +3 +20 +2 +15 +10 +1 d B r +5 +0 d B r A -5 A -10 -15 +0 -1 -2 -20 -3 -25 -30 -4 -35 -40 -140 -120 -100 -80 -60 -40 -20 -5 20 +0 50 100 200 500 1k 2k 5k 10k 20k Hz dBFS Figure 7. 48 kHz, Fade-to-Noise Linearity Figure 8. 48 kHz, Frequency Response +0 3 -10 2.5 -20 2 -30 1.5 -40 d B r -50 1 -60 500m -70 V 0 -80 -500m A -90 -100 -1 -110 -1.5 -120 -2 -130 -2.
PAGE 9
CDB4353 +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 d B r -60 d B r -70 -80 -70 -80 A A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 50 100 200 500 1k 2k 5k 10k -150 20k 20k 40k 60k Hz Figure 13. FFT (96 kHz, No Input) +0 +0 -10 -10 -20 -20 -30 -30 120k -40 d B r -50 -60 A A -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 -110 20 100k Figure 14.
PAGE 10
CDB4353 +0 3 -10 2.5 -20 2 -30 1.5 -40 -50 1 -60 d B r 500m -70 V -80 A 0 -500m -90 -100 -1 -110 -1.5 -120 -2 -130 -2.5 -140 -150 20 50 100 200 500 1k 2k 5k 10k -3 0 20k 500u Hz Figure 19. 96 kHz, Crosstalk +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 d B r -70 -70 -80 -80 A A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 50 100 200 500 1k 2k 5k 10k -150 20 20k 50 100 200 Figure 21.
PAGE 11
CDB4353 +0 +0 -10 -10 -20 -20 -30 -30 -40 d B r -40 d B r -50 -60 A A -50 -60 -70 -70 -80 -80 -90 -90 -100 -100 -110 20 50 100 200 500 1k 2k 5k 10k -110 -120 20k -100 -80 -60 -40 -20 +0 dBFS Hz Figure 25. 192 kHz, THD+N vs. Input Freq Figure 26. 192 kHz, THD+N vs.
PAGE 12
12.SCHEMATICS AND LAYOUT Indicator LEDs +3.3V Power (Optional separate VL) S/PDIF Error S/PDIF or PCM Input Selected +3.
PAGE 13
DS803DB2 13 CDB4353 Figure 32.
PAGE 14
CDB4353 DS803DB2 Figure 33.
PAGE 15
DS803DB2 15 CDB4353 Figure 34.
PAGE 16
CDB4353 DS803DB2 Figure 35.
PAGE 17
DS803DB2 17 CDB4353 Figure 36.
PAGE 18
CDB4353 13.REVISION HISTORY Release DB1 DB2 Changes Initial Release Updated block diagram on page 1 and Figure 31. Updated features and description on page 1. Updated plots in Section 11. Performance Plots. Updated Figure 32 and Figure 33. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc.