Instruction Manual

36 DS585F2
CS42526
4.6.4.5 OLM Config #5
This One-Line Mode configuration can support up to 6 channels of DAC data 2 channels of ADC data and
2 channels of S/PDIF received data and will handle up to 24-bit samples at a sampling frequency of 48 kHz
on all channels for both the DAC and ADC. The output data stream of the internal ADCs can be configured
to use the CX_SDOUT output and run at the CODEC_SP clock speeds or to use the SAI_SDOUT data
output and run at the SAI_SP rate. The CODEC_SP and SAI_SP can operate at different Fs rates.
Register / Bit Settings Description
Functional Mode Register (addr = 03h)
Set CODEC_FMx = 00,01,10
CX_LRCK can run at SSM, DSM, or QSM independent of SAI_LRCK
Set SAI_FMx = 00,01,10
SAI_LRCK can run at SSM, DSM, or QSM independent of CX_LRCK
Set ADC_SP SELx = 00,01,10
Configure ADC data to use CX_SDOUT and CODEC_SP clocks, or
SAI_SDOUT and SAI_SP cocks.
Interface Format Register (addr = 04h)
Set DIFx bits to proper serial format
Select the digital interface format when not in one line mode
Set ADC_OLx bits = 00
Set ADC operating mode to Not One Line Mode since only 2 channels of
ADC are supported
Set DAC_OLx bits = 00,01
Select DAC operating mode, see table below for valid combinations
Misc. Control Register (addr = 05h)
Set CODEC_SP M/S = 0 or 1
Set CODEC Serial Port to master mode or slave mode.
Set SAI_SP M/S = 0 or 1
Set Serial Audio Interface Port to master mode or slave mode.
Set EXT ADC SCLK = 0
External ADCs are not used. Leave bit in default state.
CX_SDOUT= ADC Data
SAI_SDOUT=ADC or
S/PDIF Data
DAC Mode
Not One-Line Mode One-Line Mode #1 One-Line Mode #2
ADC Mode
Not One-
Line Mode
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=64 Fs
SAI_LRCK=SSM/DSM/QSM
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=SSM/DSM/QSM
not valid
One-Line
Mode #1
not valid not valid not valid
One-Line
Mode #2
not valid not valid not valid
SCLK_PORT1
LRCK_PORT1
SDIN_PORT1
SCLK_PORT2
LRCK_PORT2
SDIN_PORT2
SCLK_PORT3
LRCK_PORT3
SDOUT1_PORT3
SDOUT2_PORT3
SDOUT3_PORT3
RMCK
ADCIN1
ADCIN2
SPDIF or ADC Data
ADC Data
64Fs,128Fs, 256Fs
DIGITAL AUDIO
PROCESSOR
SAI_SCLK
SAI_LRCK
SAI_SDOUT
CX_SCLK
CX_LRCK
CX_SDOUT
CX_SDIN1
CX_SDIN2
CX_SDIN3
64Fs,128Fs, 256Fs
MCLK
Figure 20. OLM Configuration #5
CS42518