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Advance Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

MAY ‘10

DS882PB1

Ultra Low Power Mobile Audio and Telephony CODEC

Product Overview

For the full datasheet, visit

www.cirrus.com/codec-datasheets/CS42L73

 Stereo ADC

 Dual Analog or Digital MIC Support

 Dual MIC Bias Generators

 Four DACs Coupled to Five Outputs

– Ground-Centered Stereo Headphone Amp.

– Ground-Centered Stereo Line Output

– Mono Ear Speaker Amplifier

– Mono 1 W Speakerphone Amplifier

– Mono Speakerphone Line Output for Stereo

Speakerphone Expansion

 Three Serial Ports with Asynchronous Sample

Rate Converters

 Digital Audio Mixing and Routing

Ultra Low Power Consumption

 3.5 mW Quiescent Headphone Playback

Applications

 Smart Phones, UMPCs, and MIDs

System Features

 Native (no PLL required) Support for 6/12/24

MHz, 13/26 MHz, and 19.2/38.4 MHz Master

Clock Rates in Add. to Typ. Audio Clock Rates

 Integrated High-efficiency Power Management

Reduces Power Consumption

– Internal LDO Regulator to Reduce Internal

Digital Operating Voltage to VL/2

– Step-down Charge Pump Provides Low

Headphone/Line Out Supply Voltage

– Inverting Charge Pump Accommodates Low

System Voltage by Providing Negative Rail

for HP and Line Amp

 Flexible Speakerphone Amplifier Powering

– 3.00 V to 5.25 V Range

– Independent Cycling

 Power Down Management

– Individual Controls for ADCs, Dig. MIC

Interface, MIC Bias Generators, Serial Ports,

and Output Amplifiers & Associated DACs

 Programmable Thermal Overload Notification

 High-speed I²C™ Control Port (400 kHz)

(Features continued on page 2)

CS42L73

Line Outputs

Pseudo Diff. Input

+VCP_FILT

-VCP_FILT

Digital Processing

Level Shifters

CS42L73

Decimator,

HPF,

Noise

Gate,

ALC,

Volume,

Mute,

Swap/Mono

Volume, Mute, Limiter

MCLK

Stereo

Multi-bit

ΔΣ DAC

MCLK

Stereo

Multi-bit

ΔΣ DAC

LDO

VD_FILT

Headphone Outputs

Pseudo Diff. Input

+VCP_FILT

-VCP_FILT

Ear Speaker Output

Speakerphone Line

Output (Right)

Speakerphone Output

(Left)

Digital MIC Interface

MCLK

Stereo

Multi-bit

ΔΣ ADC

-6 to +12 dB,

0.5 dB steps

MIC 2

MIC 1

Pseudo Diff. Input

Line Input (Left)

Line Input (Right)

Pseudo Diff. Input

+10 or

+20 dB

+10 or

+20 dB

MIC 1 Bias

MIC 2 Bias

MIC Bias Short DetectMIC Bias

Audio Serial Port

Voice Serial Port

Auxiliary Serial Port

Audio

Serial Port

SDOUT

SDIN

ASRC

Voice

Serial Port

SDOUT

ASRC

Auxiliary

Serial Port

SDIN

ASRC

SDOUT

ASRC

SDIN

ASRC

-VCP_FILT

Inverting

Step-Down

VCP +VCP_FILT

+VCP_FILT

-VCP_FILT

MCLK

MCLK1

MCLK2

Control Port

VD_FILT

Digital Mixer

Volume, Mute, Limiter

MIC2_SDET

Audio Serial Port

Voice Serial Port

Auxiliary Serial Port

MIC/Line Input Path

Summary of content (7 pages)

PAGE 1
CS42L73 Ultra Low Power Mobile Audio and Telephony CODEC Product Overview For the full datasheet, visit System Features  Native (no PLL required) Support for 6/12/24 www.cirrus.com/codec-datasheets/CS42L73  Stereo ADC  Dual Analog or Digital MIC Support  Dual MIC Bias Generators  Four DACs Coupled to Five Outputs – Ground-Centered Stereo Headphone Amp.
PAGE 2
CS42L73 Stereo Analog to Digital Features  91 dB Dynamic Range (A-wtd)  -85 dB THD+N  Independent ADC Channel Control  2:1 Stereo Analog Input MUX  Stereo Line Input     – Shared Pseudo-differential Reference Input Dual Analog MIC Inputs – Pseudo-diff. or Single-ended – Two, Independent, Programmable, Lownoise, MIC Bias Outputs – MIC Short Detect to Support Headset Button Analog Programmable Gain Amplifier (PGA) (+12 to -6 dB in 0.
PAGE 3
CS42L73 General Description The CS42L73 is a highly integrated, low-power, audio and telephony CODEC for portable applications such as smartphones and ultra mobile personal computers. The CS42L73 features a flexible clocking architecture, allowing the device to utilize reference clock frequencies of 6, 12, 24, 13, 26, 19.2, or 38.4 MHz, or any standard audio master clock.
PAGE 4
CS42L73 1. TYPICAL CONNECTION DIAGRAM CS42L73 HPOUTB 33 nF 100 Ω 33 nF 100 Ω Headphone Out Left & Right HPOUTA HPOUT_REF VBAT PMU Reset Generator LDO USB +5 V Switching Regulator +1.8 V +1.8 V VANA RESET LINEOUTB VA LINEOUTA 0.1 µF 390 Ω 390 Ω Optional LPF VCP 2.2 µF 2.2 µF +VCP_FILT -VCP_FILT 2.2 µF Line Level Out Left & Right 2200 pF C0G LINEO_REF VDIG 2200 pF C0G EAROUT+ EAROUT- Ear Speaker (Receiver) CPGND 2.2 µF FLYP VP 2.2 µF FLYC SPK_VQ VBAT 0.1 µF FLYN + 4.
PAGE 5
0.450 0.170 0.280 0.230 3.415 3.415 A A1 A2 M N b c d e X Y 0.505 0.200 0.305 2.800 2.800 0.260 0.320 0.320 0.400 3.440 3.440 MILLIMETERS NOM 0.560 0.230 0.330 0.290 3.465 3.465 MAX Y Table 1. WLCSP Package Dimensions Controlling Dimension is Millimeters. MIN Dim WAFER BACK SIDE Ball A1 Location Indicator A SIDE VIEW A2 e b 4. 1. 2. 3. e BUMP SIDE M c N d Ball A1 Controlling dimensions are in millimeters. Dimensioning and tolerances per ASME Y 14.5M-1994.
PAGE 6
0.74 0.16 0.58 0.27 4.90 4.90 A A1 A2 M N b c d e X Y 0.87 0.21 0.66 4.00 4.00 0.30 0.50 0.50 0.50 5.00 5.00 MILLIMETERS NOM Table 2. FBGA Package Dimensions Controlling Dimension is Millimeters. MIN TOP SIDE 1.00 0.26 0.74 0.37 5.10 5.10 MAX Y SIDE VIEW A2 A1 4. 1. 2. 3. e BUMP SIDE Ball A1 c N d Controlling dimensions are in millimeters. Dimensioning and tolerances per ASME Y 14.5M-1994.
PAGE 7
CS42L73 3. THERMAL CHARACTERISTICS Parameter (Notes 1 and 2) Symbol Min Typ Max Units θJA - 43 - °C/Watt θJA - 58 - °C/Watt WLCSP Package Junction to Ambient Thermal Impedance FBGA Package Junction to Ambient Thermal Impedance Notes: 1. Test Printed Circuit Board Assembly (PCBA) constructed in accordance with JEDEC standard JESD51-9. Two signal, two plane (2s2p) PCB utilized. 2. Test conducted with still air in accordance with JEDEC standards JESD51, JESD51-2A, and JESD51-8. 4.