User Manual

DS619F1 17
CS4364
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C
L
=30pF)
Notes:
17. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For F
SCK
< 1 MHz.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
sclk
-6MHz
RST
Rising Edge to CS Falling t
srs
500 - ns
CCLK Edge to CS
Falling (Note 17) t
spi
500 - ns
CS
High Time Between Transmissions t
csh
1.0 - µs
CS
Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 18) t
dh
15 - ns
Rise Time of CCLK and CDIN (Note 19) t
r2
-100ns
Fall Time of CCLK and CDIN (Note 19) t
f2
-100ns
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
csh
t
spi
t
srs
RST
Figure 5. Control Port Timing - SPI Format