User`s manual

Functional Overview of the CS485xx Chip
CS485xx Hardware User’s Manual
DS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-6
Table 1-1 lists the firmware available based on device selection. Please refer AN298, CS485xx Firmware
User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available.
1.3 Functional Overview of the CS485xx Chip
The CS485xx chip supports a maximum clock speed of 150 MHz in a 48-pin LQFP package. A high-level
functional description of the CS485xx chip is provided in this section.
1.3.1 DSP Core
The CS485xx DSP core is a general-purpose, 32-bit, fixed-point, fully programmable digital signal processor
that achieves high performance through an efficient instruction set and highly parallel architecture. The
device uses two’s complement fractional number representation, and employs busses for two data memory
spaces and one program memory space.
CS485xx core enhancements include portability of the design, speed improvement, and improvements for
synthesis, verification, and testability. Each member of the CS485xx family has different SRAM and ROM
sizes. Please refer to the CS485xx data sheet for specification details and ordering information.
1.3.2 Debug Controller (DBC)
An I
2
C slave debug controller (DBC) is integrated within the CS485xx DSP core. Two pins are reserved for
connecting a PC host to the debug port on the DSP. The debug port consists of two modules, an I
2
C slave
and a debug master. The DBC master sends dedicated signals into the DSP core to initiate debug actions
and it receives acknowledge signals from the core to indicate the requested action has been taken.
Basically, this interface allows the DBC to insert instructions into the pipeline. The core will acknowledge the
action when it determines the pipeline is in the appropriate state for the inserted action to be taken.
1.3.3 Digital Audio Output (DAO) Controller
The CS485xx has two Digital Audio Output (DAO) controllers, which contain up to 6 stereo output pins. One
DAO pin can be used as a S/PDIF transmitter. The DAO port can transmit up to 12 channels of serial audio
data in I
2
S-compatible format. The port supports sample rates (Fs) as high as 192 kHz. The port can be
configured to support two independent clock domains. The audio samples are stored in up to 12 channel
Table 1-1. Device and Firmware Selection Guide
Device Suggested Application
Channel Count
Input/Output Package
CS48520-CQZ
•Digital TV
• Portable Audio Docking Station
• Portable DVD
•DVD Mini / Receiver
• Multimedia PC Speakers
Up to 4 channel in / 4
channel out
48-pin LQFP
CS48540-CQZ
CS48540-DQZ
CS48520 features Plus:
• 8 Channel Car Audio
• Sound Bar
•DVD Receiver
Up to 8 channel in / 8
channel out
48-pin LQFP
CS48560-CQZ
CS48560-DQZ
CS4840 features Plus:Features:
• 12 channel Car Audio
• High-end Digital TV
• Dual Source/Dual Zone
•SACD
Up to 12 channel in /12
channel out
48-pin LQFP