User`s manual

vi Copyright 2009 Cirrus Logic DS734UM7
Figures
CS485xx Hardware User’s Manual
Figure 3-18. Sample Waveform for SPI Read Functional Timing ..............................................................3-21
Figure 4-1. 10-Channel DAI Port Block Diagram .........................................................................................4-3
Figure 4-2. 8-Channel DAI Port Block Diagram ...........................................................................................4-3
Figure 4-3. 6-Channel DAI Port Block Diagram ...........................................................................................4-4
Figure 4-4. 12-Channel DAI Port Block Diagram .........................................................................................4-5
Figure 4-5. I
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S format (Rising Edge Valid SCLK) .........................................................................................4-6
Figure 4-6. Left-justified Format (Rising Edge Valid SCLK) .........................................................................4-6
Figure 5-1. DSD Port Block Diagram on CS48560 ......................................................................................5-2
Figure 6-1. CS48560 DAO Block Diagram ...................................................................................................6-2
Figure 6-2. CS48540 DAO Block Diagram ...................................................................................................6-3
Figure 6-3. CS48520 DAO Block Diagram ...................................................................................................6-3
Figure 6-4. I
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S Compatible Serial Audio Formats (Rising Edge Valid DAO_SCLK) ....................................6-4
Figure 6-5. Left-justified Digital Audio Formats (Rising Edge Valid DAO_SCLK) ........................................6-4
Figure 6-6. One-line Data Mode Digital Audio Formats ...............................................................................6-5
Figure 7-1. Typical Connection for Watchdog Timer Alarm .........................................................................7-2
Figure 8-1. SPI Slave, 10 channels of Digital Audio Input, All Audio Clocks
Synchronous to S/PDIF RX ...........................................................................................................................8-2
Figure 8-2. I
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C Slave, 10 Channels of Digital Audio Input, Dual Clock Domains,
Output Audio Clocks Synchronous to HDMI Rx ............................................................................................8-3
Figure 8-3. I
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C Slave, 12 Channels of Digital Audio Input, Single Clock Domain,
All Audio Clocks Synchronous to XTAL_OUT ...............................................................................................8-4
Figure 8-4. I
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C master, 10 Channels of Digital Audio Input, All Audio Clocks
Synchronous to S/PDIF Rx ...........................................................................................................................8-5
Figure 8-5. SPI Slave, 10 Channels of Digital Audio Input,
All Audio Clocks Synchronous to S/PDIF Rx ................................................................................................8-6
Figure 8-6. SPI Slave, 10 Channels of Digital Audio Input,
Dual Clock Domains, Output Audio Clocks Synchronous to HDMI Rx .........................................................8-7
Figure 8-7. SPI Slave, 12 Channels of Digital Audio Input, Single
Clock Domain, All Audio Clocks Synchronous to XTAL_OUT ......................................................................8-8
Figure 8-8. SPI Master, 10 Channels of Digital Audio Input, All
Audio Clocks Synchronous to S/PDIF Rx. ....................................................................................................8-9
Figure 8-9. PLL Filter Topology ..................................................................................................................8-12
Figure 8-10. Crystal Oscillator Circuit Diagram ..........................................................................................8-13
Figure 8-11. 48-Pin LQFP Pin Layout of CS48560 ....................................................................................8-15
Figure 8-12. 48-Pin LQFP Pin Layout of CS48540 ....................................................................................8-16
Figure 8-13. 48-Pin LQFP Pin Layout of CS48520 ....................................................................................8-17