User Manual

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Audio Decoder DSP Family with

Dual 32-bit DSP Engine Technology

CS4953xx Data Sheet

http://www.cirrus.com

FEATURES

 Multi-standard 32-bit Audio Decoding plus Post

processing

 Supports legacy audio formats and a wide array of post-

processing

— Dolby Digital

EX, Dolby Pro Logic

II, IIx, IIz 7.1,

Dolby Headphone

2, Dolby Virtual Speaker

Dolby

Volume

(original), Dolby

Volume 258

™

(lite),

Audistry

— DTS-ES 96/24

™

Discrete 7.1, DTS-ES

™

Discrete 7.1,

DTS-ES

™

Matrix 6.1, DTS Neo:6

, DTS Neural

Surround

™

DTS Surround Sensation Speaker

— MPEG-2 AAC

™

LC 5.1

—SRS

Circle Surround

II, SRS Circle Surround Auto,

SRS Circle Surround Decoder Optimized, SRS

TruVolume

™

7.1 (V 2.1.0.0), SRS TruSurround

HD/HD4

SRS WOW HD

™

, SRS CS Headphone

™

SRS Circle Cinema 3D

™

, SRS Studio Sound HD

™

—THX

Ultra2

™

, THX Select2

™

 Cirrus Logic’s Applications Library

— Cirrus Original Multi-Channel Surround 2 (COMS2),

Cirrus Band XpandeR

™

, Cirrus Virtualization

Technology (CVT), Cirrus Intelligent Room Calibration

2 (IRC2), Cirrus Bass Enhancement (CBE)

— Crossbar Mixer, Signal Generator

— Advanced Post-Processors including: 7.1 Bass

Manager Quadruple Crossover, Tone Control, 11-

Band Parametric EQ, Delay, 2:1/4:1 Decimator,

1:2/1:4 Upsampler

 Up to 12 Channels of 32-bit Serial Audio Input

 16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx

 Two SPI

™

Ports

 Customer Software Security Keys

 Large On-chip X, Y, and Program RAM & ROM

 SDRAM and Serial Flash Memory Support

The CS4953xx DSP family are the enhanced versions of the

CS495xx DSP family with higher overall performance and

lower system cost. The CS4953xx includes all mainstream

audio processing codes in on-chip ROM. This saves external

memory for code storage. In addition, the intensive decoding

tasks of Dolby Digital Surround EX

, AAC multi-channel,

DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone

can be accomplished without the expense of external

SDRAM memory.

With larger internal memories than the CS495xx, the

CS49531x is designed to support up to 150 ms per channel

of lip-sync delay. With 150 MHz internal clock speed, the

CS4953xx supports the most demanding post-processing

requirements. It is also designed for easy upgrading.

Customers currently using the CS495xx can upgrade to the

CS4953xx with minor hardware and software changes.

Ordering Information

See page 28 for ordering information.

Coyote 32-bit

DSP A

Coyote 32-bit

DSP B

Ext. Memory Controller

S/PDIF

X Y P X Y

Serial

Control 1

16 Ch PCM

Audio Out

Serial

Control 2

Parallel

Control

GPIO Debug

STC

TMR1

TMR2

PLL

S/PDIF

12 Ch PCM

Audio In

Summary of content (37 pages)

PAGE 1
CS4953xx Data Sheet FEATURES Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology  Multi-standard 32-bit Audio Decoding plus Post processing  Supports legacy audio formats and a wide array of postprocessing — Dolby Digital® EX, Dolby Pro Logic® II, IIx, IIz 7.1, Dolby Headphone® 2, Dolby Virtual Speaker® 2, Dolby Volume® (original), Dolby Volume 258™ (lite), Audistry® — DTS-ES 96/24™ Discrete 7.1, DTS-ES™ Discrete 7.1, DTS-ES™ Matrix 6.
PAGE 2
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Table of Contents 1 Documentation Strategy ............................................................................................................4 2 Overview .....................................................................................................................................4 2.1 Migrating from CS495xx(2) to CS4970x4 ................................................................................................. 5 2.2 Licensing ....
PAGE 3
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9.1 128-Pin LQFP Package Drawing ........................................................................................................... 29 9.2 144-Pin LQFP Package Drawing ........................................................................................................... 30 10 Revision History .....................................................................................................................31 List of Figures Figure 1.
PAGE 4
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 1 Documentation Strategy The CS4953xx data sheet describes the CS4953xx family of multichannel audio decoders. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS4953xx family of processors. Table 1.
PAGE 5
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 2.1 Migrating from CS4953x3 to CS4953x4 • The recommended way to boot the DSP for normal operation is “master boot”. Refer to Chapter 1 of the CS4953x4/CS4970x4 System Designer’s Guide. CS4953x4 supports slave boot mode as well (used for programming the serial flash with the DSP code, through the SCP2 port). • CS4953x4 DSPs are only available in 128 pin package. • The serial flash chip select pin used is pin 14 (GPIO0) for master boot.
PAGE 6
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Table 2. Device and Firmware Selection Guide1 Device PreProcess Decode Processor (DSP-A)2 Matrix-processor (DSP-A)2 Virtualizerprocessor (DSP-B)2 Post-processor (DSP-B)2 Dolby Pro Logic II/IIx/IIz 7.
PAGE 7
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4 Hardware Functional Description 4.1 Coyote 32-bit DSP Core The CS4953xx is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers.
PAGE 8
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.2 On-chip DSP Peripherals 4.2.1 Digital Audio Input Port (DAI) The 12-channel (6-line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM or IEC61937. Up to 32-bit word lengths are supported. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain.
PAGE 9
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 4.3.2 Termination Requirements Open-drain pins on the CS4953xx must be pulled high for proper operation. Refer to the CS4953xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset.
PAGE 10
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.2 Recommended Operating Conditions (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter Core supply PLL supply I/O supply |VDDA – VDDIO| DC power supplies: Symbol VDD VDDA VDDIO Min 1.71 3.13 3.13 Typ 1.8 3.3 3.3 0 Max 1.89 3.46 3.
PAGE 11
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.5 Thermal Data (144-pin LQFP) Parameter Symbol Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 Min Typ Max — — 48 40 — — — — .39 .33 — — Min Typ Max — — 53 44 — — — — .45 .39 — — θja Unit °C / Watt ψjt °C / Watt 5.
PAGE 12
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.7 Switching Characteristics—RESET Parameter Symbol Min Max Unit Trstl 1 — μs All bidirectional pins high-Z after RESET low Trst2z /m 100 ns Configuration pins setup before RESET high Trstsu 50 — ns Configuration pins hold after RESET high Trsthld 20 — ns RESET minimum pulse width low RESET# HS[3:0] All Bidirectional Pins Trstsu Trsthld Trst2z Trstl Figure 1. RESET Timing 5.
PAGE 13
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.9 Switching Characteristics — Internal Clock Parameter Internal DCLK frequency1 CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DVZ Internal DCLK period1 CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DVZ Symbol Min Max Unit Fdclk — 130 MHz — Fxtal Fxtal Fxtal Fxtal Fxtal 150 150 150 131 131 — DCLKP — 7.7 ns — 6.7 6.7 6.7 7.63 7.63 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal — 1.
PAGE 14
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.
PAGE 15
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family tspicss SCP_CS tspickl 1 0 2 6 7 0 A0 R/W MSB 5 6 7 tspicsh SCP_CLK fspisck SCP_MOSI tspickh A6 A5 LSB tspidsu tspidh SCP_MISO tspidov tspicsdz MSB LSB tspiirqh tspiirql SCP_IRQ tspibsyl SCP_BSY Figure 3.
PAGE 16
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.11 Switching Characteristics — Serial Control Port - SPI Master Mode Parameter Symbol Min Typical Max Units fspisck — — Fxtal/2 MHz tspicss — 11*DCLKP + (SCP_CLK PERIOD)/2 — ns SCP_CLK low time tspickl 16.9 — — ns SCP_CLK high time tspickh 16.
PAGE 17
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode Parameter SCP_CLK frequency 1 Symbol Min Typical Max Units fiicck — — 400 kHz SCP_CLK low time tiicckl 1.25 — — µs SCP_CLK high time tiicckh 1.25 — — µs tiicckcmd 1.25 — — µs START condition to SCP_CLK falling tiicstscl 1.25 — — µs SCP_CLK falling to STOP condition tiicstp 2.
PAGE 18
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.13 Switching Characteristics — Serial Control Port - I2C Master Mode Parameter SCP_CLK frequency Symbol Min Max Units 1 fiicck — 400 kHz SCP_CLK low time tiicckl 1.25 — µs SCP_CLK high time tiicckh 1.25 — µs tiicckcmd 1.25 — µs START condition to SCP_CLK falling tiicstscl 1.25 — µs SCP_CLK falling to STOP condition tiicstp 2.
PAGE 19
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.
PAGE 20
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family PCP_A[3:0] t iah PCP_D[7:0] LSP t ias t idhr t idd PCP_CS MSP t icdr t idis PCP_WR t irpw t ird t irdtw PCP_RD t irdirqh PCP_IRQ Figure 7. Parallel Control Port - Intel Slave Mode Read Cycle PCP_A[3:0] t iah PCP_D[7:0] t ias LSP MSP t idhw PCP_CS t icdw PCP_RD t idsu t iwpw t iwd t iwtrd PCP_WR t iwrbsyl PCP_BSY Figure 8.
PAGE 21
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.
PAGE 22
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family PCP_A[3:0] t mas t mah LSP PCP_AD[7:0] MSP t mdhr PCP_CS t mdd t mrwsu t mcdr t mdis t mrwhld PCP_WR t mrpw t mrdtw t mrd PCP_DS tmrwirqh PCP_IRQ Figure 9. Parallel Control Port - Motorola Slave Mode Read Cycle Timing PCP_A[3:0] t mas PCP_AD[7:0] t mah LSP t mdsu MSP t mdhw PCP_CS t mcdw t mrwhld t mwpw PCP_WR t mrwsu t mwd t mwtrd PCP_DS tmrwirql PCP_IRQ Figure 10.
PAGE 23
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.
PAGE 24
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 5.
PAGE 25
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family tdaosclk DAO_LRCLK DAO_LRCLK tdaoslrts DAO_SCLK DAO_SCLK tdaosclk tdaosstlr DAO_Dx tdaosdv DAO_Dx Figure 14. Digital Audio Output Timing, Slave Mode 5.18 Switching Characteristics — SDRAM Interface Refer to Figure 15 through Figure 18. (SD_CLKOUT = SD_CLKIN) Parameter Symbol Min Typical Max Unit tsdclkh 2.3 — — ns SD_CLKIN low time tsdclkl 2.
PAGE 26
DS705F2 SD_CLKOUT t sdcmdv t sdclkrf t sdcmdh SD_CS SD_RAS SD_CAS SD_WE tsddqh t sddqv SD_DQMn 11 00 SD_An t sdav tsddsu CAS=2 SD_Dn tsddh LSP0 LSP1 MSP0 MSP1 LSP2 MSP2 LSP3 MSP3 SD_CLKIN t sdclkl t sdclkh Figure 15. External Memory Interface - SDRAM Burst Read Cycle SD_CLKOUT t sdcmdv tsdcmdh SD_CS SD_RAS SD_CAS LSP 0 SD_Dn MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 t sdav SD_An SD_DQMn 00 tsddqv 11 t sddqh 26 Figure 16.
PAGE 27
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family SD_CLKOUT tsdcmdv tsdcmdv t sdcmdh SD_CS SD_RAS SD_CAS SD_WE SD_DQMn SD_An SD_Dn Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle SD_CLKOUT tsdcmdv t sdcmdh SD_CS SD_RAS SD_CAS SD_WE SD_DQMn SD_An OPCODE SD_Dn Figure 18.
PAGE 28
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 6 Ordering Information The CS4953xx family part number is described as follows: CS495NNI-XYZ where NN - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free Table 5. Ordering Information Part No. Status CS495303-CVZ CS495303-CVZR Temp.
PAGE 29
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 7 Environmental, Manufacturing, and Handling Information Table 6.
PAGE 30
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 8 Device Pinout Diagrams 8.
PAGE 31
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 8.2 128-pin LQFP Pinout Diagrams (CS495304/CS495314) SD_A10, EXT_A10 SD_BA0, EXT_A13 SD_BA1, EXT_A14 105 GNDIO5 SD_WE SD_CAS SD_RAS EXT_A15 110 SD_CS VDD5 EXT_A16 EXT_A17 EXT_A18 115 GND5 EXT_A19 EXT_OE EXT_CS1 120 VDDIO6 GNDIO6 RESET GPIO33, SCP1_MOSI GPIO34, SCP1_MISO, SCP1_SDA GPIO35, SCP1_CLK 125 VDD6 GND6 GPIO37, SCP1_BSY, PCP_BSY The CS495304/CS495314 DSP with a 128-pin package is recommended for new designs.
PAGE 32
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 8.
PAGE 33
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9 Package Mechanical Drawings 9.1 128-pin LQFP Package Drawing D D1 E E1 1 e b ∝ A A1 L Figure 22. 128-pin LQFP Package Drawing Table 7. 128-pin LQFP Package Characteristics MILLIMETERS INCHES DIM A A1 b D D1 E E1 e q L L1 MIN NOM MAX MIN NOM MAX — 0.05 0.17 — — 0.22 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 3.5 0.60 1.00 REF 1.60 0.15 0.27 — .002” .007” .063” .006” .011” 7° 0.75 0° .018” — — .009” .866” .787” .630” .551” .
PAGE 34
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 9.2 144-pin LQFP Package Drawing E E1 D D1 Notes: 1. Controlling dimension is millimeter. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. e b SEATING PLANE ddd M B B L1 θ A A1 L Figure 23. 144-pin LQFP Package Drawing Table 8. 144-pin LQFP Package Characteristics MILLIMETERS INCHES DIM A A1 b D D1 E E1 e q L L1 MIN NOM MAX MIN NOM MAX — 0.05 0.17 — — 0.22 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.50 BSC — 0.60 1.00 REF 1.60 0.
PAGE 35
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family 10 Revision History Revision Date Changes A1 Advance release. February, 2006 A2 June, 2006 Updated part numbers for ordering (Tables 5 & 6), Updated VOH and VOL specification to include the current load used for testing A3 July, 2006 Updated part numbers for ordering (Tables 5 & 6). Updated text in sections 3 and 4. Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh, and Tspidov timing.
PAGE 36
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Revision Date Changes PP8 April, 2011 Added Tj conditions to Section 5.2. Changed 500 ma to 350 ma in Section 5.4. Removed references to DSD. Updated legal statement. Updated features list. Added notes to Section 5.10. Updated Section 5.16 “Switching Characteristics — Digital Audio Slave Input Port” on page 23 Updated Section 5.17 “Switching Characteristics — Digital Audio Output Port” on page 24. PP9 August, 2011 In section Section 5.
PAGE 37
CS4953xx Data Sheet 32-bit Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).