Personal Computer User Manual

ManualsBrandsCompaq ManualsDesktop4000N

Technical

Reference

Guide

for

Compaq Deskpro 4000N and 4000S Personal Computers

Summary of content (196 pages)

PAGE 1
Technical Reference Guide for Compaq Deskpro 4000N and 4000S Personal Computers
PAGE 2
This hardcopy is designed to be placed into a standard 3-ring binder. Provided below is a title block that can be copied and cut out and placed into the slip or taped onto the edge of the binder.
PAGE 3
Technical Reference Guide NOTICE The information in this document is subject to change without notice. COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL ERRORS OR OMISSIONS HEREIN; NOR FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL. IT IS THE RESPONSIBILITY OF MANUFACTURERS TO ENSURE THAT DEVICES DESIGNED TO BE USED WITH COMPAQ PRODUCTS COMPLY WITH FCC CLASS B EMISSIONS REQUIREMENTS.
PAGE 4
Technical Reference Guide ii Compaq Deskpro 4000N and 4000S Personal Computers First Edition – September 1997
PAGE 5
Technical Reference Guide TABLE OF CONTENTS CHAPTER 1 INTRODUCTION............................................................................................................. 1.1 ABOUT THIS GUIDE ........................................................................................................... 1-1 1.1.1 USING THIS GUIDE ..................................................................................................... 1-1 1.1.2 ADDITIONAL INFORMATION SOURCES.....................................
PAGE 6
Technical Reference Guide CHAPTER 4 SYSTEM SUPPORT......................................................................................................... 4.1 INTRODUCTION.................................................................................................................. 4-1 4.2 PCI BUS OVERVIEW ........................................................................................................... 4-2 4.2.1 PCI CONNECTOR....................................................................
PAGE 7
Technical Reference Guide 5.6 KEYBOARD/POINTING DEVICE INTERFACE ............................................................... 5-28 5.6.1 KEYBOARD INTERFACE OPERATION ................................................................... 5-28 5.6.2 POINTING DEVICE INTERFACE OPERATION ....................................................... 5-30 5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING ......................... 5-30 5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR................................
PAGE 8
Technical Reference Guide 8.4 CLIENT MANAGEMENT SUPPORT................................................................................... 8-5 8.4.1 SYSTEM ID................................................................................................................... 8-7 8.4.2 SYSTEM INFORMATION TABLE ............................................................................... 8-7 8.4.3 TEMPERATURE SENSOR..........................................................................................
PAGE 9
Technical Reference Guide C.3 SCANNER DESCRIPTION .................................................................................................C-14 C.3.1 SCANNER OPERATION.............................................................................................C-15 C.3.2 SCANNER INTERFACE .............................................................................................C-18 C.3.3 SCANNER SPECIFICATIONS/REQUIREMENTS......................................................
PAGE 10
Technical Reference Guide LIST OF FIGURES FIGURE 2–1. COMPAQ DESKPRO 4000S PERSONAL COMPUTER WITH MONITOR ....................................... 2-1 FIGURE 2–2. CABINET LAYOUT, FRONT VIEW ....................................................................................... 2-4 FIGURE 2–3. CABINET LAYOUT, REAR VIEW ......................................................................................... 2-5 FIGURE 2–4. CHASSIS LAYOUT, TOP VIEW .............................................................
PAGE 11
Technical Reference Guide LIST OF TABLES TABLE 1–1. ACRONYMS AND ABBREVIATIONS ....................................................................................... 1-3 TABLE 2–1. ARCHITECTURAL COMPARISON............................................................................................. 2-8 TABLE 2–2. SUPPORT CHIPSETS .......................................................................................................... 2-11 TABLE 2–3. GRAPHICS SUBSYSTEM OVERVIEW ............................
PAGE 12
Technical Reference Guide TABLE 5–12. TABLE 5–13. TABLE 5–14. TABLE 5–15. TABLE 5–16. TABLE 5–17. TABLE 5–18. TABLE 5–19. TABLE 5–20. TABLE 5–21. TABLE 5–22. SERIAL INTERFACE CONTROL REGISTERS ........................................................................ 5-17 PARALLEL INTERFACE CONFIGURATION REGISTERS ......................................................... 5-23 PARALLEL INTERFACE CONTROL REGISTERS ...................................................................
PAGE 13
Technical Reference Guide Chapter 1 INTRODUCTION 1. Chapter 1 INTRODUCTION 1.1 ABOUT THIS GUIDE This guide provides technical information about the Compaq Deskpro 4000N and 4000S Personal Computers. This document includes information regarding system design, function, and features that can be used by programmers, engineers, technicians, and system administrators. 1.1.1 USING THIS GUIDE This guide consists of chapters and appendices.
PAGE 14
Chapter 1 Introduction 1.2 NOTATIONAL CONVENTIONS 1.2.1 VALUES Hexadecimal values are indicated by the letter “h” following an alpha-numerical value. Binary values are indicated by the letter “b” following a value of ones and zeros. Memory addresses expressed as “SSSS:OOOO” (SSSS = 16-bit segment, OOOO = 16-bit offset) can be assumed as a hexadecimal value. Values that have no succeeding letter can be assumed to be decimal. 1.2.
PAGE 15
Technical Reference Guide 1.3 COMMON ACRONYMS AND ABBREVIATIONS Table 1-1 lists the acronyms and abbreviations used in this guide. Table 1–1. Acronyms and Abbreviations Table 1-1.
PAGE 16
Chapter 1 Introduction Table 1-1.
PAGE 17
Technical Reference Guide Table 1-1.
PAGE 18
Chapter 1 Introduction Table 1-1.
PAGE 19
Technical Reference Guide Chapter 2 SYSTEM OVERVIEW 2. 2.1 Chapter 2 SYSTEM OVERVIEW INTRODUCTION The Compaq Deskpro 4000N and 4000S Personal Computers are based on Pentium microprocessors featuring MMX technology and designed with an emphasis on speed, storage capacity, and multimedia compatibility to meet the requirements of the business environment. These models feature architectures incorporating the PCI and ISA buses.
PAGE 20
Chapter 2 System Overview 2.2 FEATURES This section describes the standard and distinguishing features. 2.2.
PAGE 21
Technical Reference Guide 2.2.2 MODEL DIFFERENCES Deskpro 4000N PCI connector: 1 ISA connector: none OS installed: Windows NT 4.0 Remote boot support: Yes Diskette drive installed: No Hard drive size: 1.6 or 2.1 GB CD-ROM support: No 2.2.3 Deskpro 4000S 1 (shared slot) 1 (shared slot) Windows 95 No Yes 2.
PAGE 22
Chapter 2 System Overview 2.3 MECHANICAL DESIGN This section illustrates the layout used by the formfactor. In addition, this section includes the layout of the system board. 2.3.1 CABINET LAYOUT 4 5 6 1 2 3 Item 1 2 3 4 5 6 Function Power Switch Power-On Light Hard Drive Activity Light 1.44 MB Diskette Drive (3.5” Drive) [1] 1/3 Height Drive Bay (3.5” or 5.25” Drive) [2] 1/3 Height Drive Bay (3.5” or 5.25” Drive) NOTES: [1] Deskpro 4000S only [2] Front panel access on 4000S only. Figure 2–2.
PAGE 23
Technical Reference Guide 2 1 Item 1 2 3 4 5 6 7 8 9 10 11 12 4 3 6 5 7 8 9 10 12 11 Function AC Line In Connector Line Voltage Select Switch Universal Serial Bus Interface port 1 Universal Serial Bus Interface port 2 Parallel Interface Connector Serial Interface Connector B Serial Interface Connector A Network Interface AUI Connector Network Interface RJ-45 Connector Mouse Connector Keyboard Connector Monitor Interface Figure 2–3.
PAGE 24
Chapter 2 System Overview 2.3.2 CHASSIS LAYOUT ISA Combo Slot 1 [1] PCI Combo Slot 1 Slots On Riser Card, Rear View Back Power Supply System Board Drive Bays Front NOTES: [1] Deskpro 4000S only Figure 2–4.
PAGE 25
Technical Reference Guide 2.3.
PAGE 26
Chapter 2 System Overview 2.4 SYSTEM ARCHITECTURE The Compaq Deskpro 4000N and 4000S Personal Computers featuring MMX technology are based on a Pentium MXX microprocessor matched with a support chipset that is complimentary in design. Both the “N” and “S” systems share the same basic architecture (Figure 2-7), which utilizes three main buses: the Host bus, the Peripheral Component Interconnect (PCI) bus, and the Industry Standard Architecture (ISA) bus.
PAGE 27
Technical Reference Guide 64-Bit Host Bus Mem. Bus System Memory North Bridge Microprocessor and Cache Memory Graphics Subsystem 32-Bit PCI Bus 0 PCI Connector Pri. IDE I/F EIDE Hard Drive Sec. IDE I/F CD-ROM South Bridge 8-/16-Bit ISA Bus USB I/F (2) X-Bus BIOS ROM ISA Connector [1] EIDE Hard Drive PC 87307 I/O Controller Keyboard/ Mouse I/F Diskette I/F Serial I/F (2) Parallel I/F Power Supply NOTES: CD models only. [1] Deskpro 4000S only. Figure 2–6.
PAGE 28
Chapter 2 System Overview 2.4.1 MICROPROCESSOR The Compaq Deskpro 4000N and 4000S Personal Computers feature the Pentium MMX microprocessor that is backward-compatible with software written for x86-type processors. The Pentium MMX microprocessor includes a 32 KB L1 cache and extensions to the instruction set that provide higher performance for processing graphics and video code. The microprocessor is mounted in a ZIF type-7 socket that allows replacing and/or upgrading.
PAGE 29
Technical Reference Guide 2.4.3 SUPPORT CHIPSET Table 2-2 shows the chipsets used for the Deskpro 4000N and 4000S systems. Table 2–2. Support Chipsets Table 2-2. Support Chipsets Function Host/PCI (North) Bridge: System Controller Data Buffer PCI/ISA (South) Bridge: EIDE Controller DMA Controller Interrupt Controller Timer/Counter NMI Registers Reset Control Reg. USB I/F I/O Controller: Keyboard I/F Diskette I/F Serial I/F Parallel I/F RTC/CMOS Mem. GPIO Ports 2.4.
PAGE 30
Chapter 2 System Overview 2.4.6 UNIVERSAL SERIAL BUS INTERFACE Two Universal Serial Bus (USB) ports are included, each providing a high speed interface for future systems and/or peripherals. The USB interface operates at 12 Mbps and provides hot plugging/unplugging (Plug ’n Play) functionality. 2.4.7 GRAPHICS SUBSYSTEM The graphics subsystem is integrated on the system board and operates off the PCI bus. The subsystem is based on the S3 Trio64 V2/GX controller and includes two megabytes of SGRAM.
PAGE 31
Technical Reference Guide 2.5 SPECIFICATIONS This section includes the environmental, electrical, and physical specifications for the Compaq Deskpro 4000N and 4000S Series Personal Computers. Table 2–4. Environmental Specifications Table 2-4. Environmental Specifications Parameter Operating o o o o Air Temperature 50 to 95 F (10 to 35 C) Shock N/A Vibration 0.
PAGE 32
Chapter 2 System Overview Table 2–7. Diskette Drive Specifications Table 2-7. Diskette Drive Specifications Paramemter Media Type Height Bytes per Sector Sectors per Track: High Density Low Density Tracks per Side: High Density Low Density Read/Write Heads Average Access Time: Track-to-Track (high/low) Average (high/low) Settling Time Latency Average Measurement 3.5 in 1.44 MB/720 KB diskette 1/3 512 18 9 80 80 2 3 ms/3 ms 94 ms/94ms 15 ms 100 ms Table 2–8. 8x CD-ROM Drive Specifications Table 2-8.
PAGE 33
Technical Reference Guide Table 2–9. Hard Drive Specifications Table 2-9. Hard Drive Specifications Parameter Interface: Drive Type: Drive Size: Transfer Rate Heads: Interface: Seek Time (w/settling) Single Track: Average: Full Stroke: Disk RPM: EDMA Support: PIO Support: Power Mode Command Support: Drive Fault Prediction: 1.6 GB EIDE 65 5.25 in 2.1 GB EIDE 65 5.25 in 94.0 Mb/s 16.7 MB/s 27.2-55 Mb/s 16.7 MB/s 2.0 ms 11.0 ms 25.0 ms 4500 Mode 2 Mode 4 Yes SMART II 2.0 ms 12.0 ms 22.
PAGE 34
Chapter 2 System Overview This page is intentionally blank.
PAGE 35
Technical Reference Guide Chapter 3 PROCESSOR/ MEMORY SUBSYSTEM 3. Chapter 3 PROCESSOR/MEMORY SUBSYSTEM 3.1 INTRODUCTION This chapter describes the processor/cache memory subsystem of the Compaq Deskpro 4000N and 4000S Series of Personal Computers. This chapter includes the following topics: ♦ ♦ Pentium MMX-based processor/memory subsystem [3.2] page 3-2 Klamath-based processor/memory subsystem [3.4] page 3-12 Table 3-1 lists the highlights of the processor/memory architecture. Table 3–1.
PAGE 36
Chapter 3 Processor/Memory Subsystem 3.2 PENTIUM MMX-BASED PROCESSOR/MEMORY SUBSYSTEM The processor/memory subsystem is based on the Pentium MMX microprocessor, a 512-KB or 1MB secondary cache, and a VT82C595 system controller (Figure 3-1). Pentium MMX Microprocessor Memory/PCI Data Buffer () 256-KB Secondary Cache 64-Bit Host Bus Cntl Cntl System Memory J7 J8 16-MB DIMM DIMM Mem. Data Bus Cache/ Memory/PCI Controller (VT82C595) Mem. Addr. 32-bit PCI Bus Optional module Figure 3–1.
PAGE 37
Technical Reference Guide 3.2.1 PENTIUM MMX MICROPROCESSOR The Pentium MMX microprocessor is software-compatible with earlier generation x86 microprocessors but provides significantly higher performance due to both higher processing speed and enhanced design (Figure 3-2.). Pentium MMX Microprocessor CPU w/MMX 32-KB Cache Branch Prediction Dual Pipeline Math Coproc. Figure 3–2.
PAGE 38
Chapter 3 Processor/Memory Subsystem 3.2.2 BUS/PROCESSING SPEED SELECT The Pentium MMX-based system board includes a four-position DIP switch (SW1) that is used to select the Host bus frequency and the processing frequency of the system. The SW1 positions 2 and 3 control the Bus Fraction (BF0, BF1) signals to the CPU, which determines the bus-to-core speed ratio.
PAGE 39
Technical Reference Guide 3.2.4 SYSTEM MEMORY The system board contains two 168-pin DIMM sockets for system memory. This system is designed for using SDRAM DIMMs. As shipped from the factory the standard configuration may be 16 or 32 megabytes installed. The addition of 16-, or 32-, 64-, or 128-MB DIMMs allows the expansion of system memory up to a maximum of 256 megabytes. Single or double-sided DIMMs may be used. It is strongly recommended to use DIMMs with gold-plated contacts.
PAGE 40
Chapter 3 Processor/Memory Subsystem Table 3–5. SPD Address Map (SDRAM DIMM) Table 3-5. SPD Address Map (SDRAM DIMM) Byte 0 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30, 31 32..61 NOTES: Description No. of Bytes Written Into EEPROM Total Bytes (#) In EEPROM Memory Type No. of Row Addresses On DIMM No. of Column Addresses On DIMM No. of Module Banks On DIMM Data Width of Module Voltage Interface Standard of DIMM Cycletime @ Max CAS Latency (CL) Access From Clock Config.
PAGE 41
Technical Reference Guide Figure 3-3 shows the system memory map. FFFF FFFFh FFFC 0000h FFFB FFFFh 8100 0000h 80FF FFFFh 8000 0000h 7FFF FFFFh Host, PCI Area 1000 0000h FFDF FFFFh 1000 0000h 0FFF FFFFh 0400 0000h 03FF FFFFh 0100 0000h Host, PCI, ISA Area 00FF FFFFh 0010 0000h 000F FFFFh 000F 0000h 000E FFFFh 000E 0000h 000D FFFFh 4 GB High BIOS Area (256 KB) PCI Memory (2130 MB) ISA Memory-Mapped Devices (16 MB) PCI Memory (1792 MB) Op.TSEG (Cacheable) (.1, .25, .5, 1 MB) Op.
PAGE 42
Chapter 3 Processor/Memory Subsystem 3.2.5 SUBSYSTEM CONFIGURATION The VT82C595 component provides the configuration function for the processor/memory subsystem. Table 3-6 lists the configuration registers used for setting and checking such parameters as cache (L2) control, system memory control, and PCI bus operation. These registers reside in the PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2. Table 3–6.
PAGE 43
Technical Reference Guide Chapter 4 SYSTEM SUPPORT 4. Chapter 4 SYSTEM SUPPORT 4.1 INTRODUCTION This chapter covers subjects dealing with basic system architecture and covers the following topics: ♦ ♦ ♦ ♦ ♦ ♦ PCI bus overview (4.2) page 4-2 ISA bus overview (4.3) page 4-11 System clock distribution (4.4) page 4-23 Real-time clock and configuration memory (4.5) page 4-24 I/O map and register accessing (4.6) page 4-41 System management support (4.
PAGE 44
Chapter 4 System Support 4.2 PCI BUS OVERVIEW NOTE: This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.1. This system implements a 32-bit Peripheral Component Interconnect (PCI) bus. The PCI bus uses a shared address/data bus design. On the first clock cycle of a PCI bus transaction the bus carries address information.
PAGE 45
Technical Reference Guide 4.2.1 PCI CONNECTOR B94 B62 B1 A1 A62 A94 NOTE: See caution below. Figure 4–2. 32-Bit PCI Bus Connector (32-Bit Type) Table 4–1. 32-Bit PCI Bus Connector Pinout Table 4-1. PCI Bus Connector Pinout Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -NOTE: B Signal -12 VDC TCK GND TDO +5 VDC +5 VDC INTBINTDPRSNT1RSVD PRSNT2GND GND RSVD GND CLK GND REQ+5 VDC AD31 AD29 GND AD27 AD25 +3.3 VDC C/BE3AD23 GND AD21 AD19 +3.
PAGE 46
Chapter 4 System Support 4.2.2 PCI BUS MASTER ARBITRATION The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device that is the recipient of a transaction. Request (REQ), Grant (GNT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus.
PAGE 47
Technical Reference Guide 4.2.3 PCI BUS TRANSACTIONS The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle.
PAGE 48
Chapter 4 System Support Figure 4-3 shows how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11> determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which acts as a “chip select” function for the PCI device to be configured. 31 30 24 23 Reserved Register 0CF8h 16 15 11 10 8 7 2 1 0 Bus Device Function Register 0 0 Number Number Number Index Results in: 31 AD31..0 w/Type 0 Config.
PAGE 49
Technical Reference Guide Table 4–4. PCI Function Configuration Acces Table 4-4. PCI Function Configuration Access PCI Function Host/PCI Bridge PCI/ISA Bridge IDE Interface USB Interface ACPI Cntlr. Graphics Controller Network Interface Controller Device No. 0 7 7 7 7 15 16 Function No. 0 0 1 2 3 0 0 The register index (CF8h, bits <7..2>)identifies the 32-bit location within the configuration space of the PCI device to be accessed.
PAGE 50
Chapter 4 System Support Table 4–5. PCI Device Identification Table 4-5. PCI Device Identification PCI Device VT82C595 (North Bridge) VT82C586 (South Bridge): PCI/ISA Bridge (Function 0) EIDE Controller (Function 1) USB I/F (Function 2) ACPI Cntlr (Function 3) Network Interface Controller Graphics Controller Vender ID 1106h Device ID 0595h 1106h 1106h 1106h 1106h 0E11h 5333h 0586h 0571h 3038h 3040h B011h 8901h 4.2.3.3 Special Cycles There are two types of special cycles that may occur on the PCI bus.
PAGE 51
Technical Reference Guide 4.2.5 PCI INTERRUPT MAPPING The PCI bus provides for four interrupt signals; INTA-, INTB-, INTC-, and INTD-. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots. In order to minimize latency, INTA-..
PAGE 52
Chapter 4 System Support 4.2.6 PCI CONFIGURATION PCI bus operations, especially those that involve ISA bus interaction, require the configuration of certain parameters such as PCI IRQ routing, top of memory accessable by ISA, SMI generation, and clock throttling characteristics. These parameters are handled by the PCI/ISA bridge function (PCI function #0) of the South Bridge component and configured through the PCI configuration space registers listed in Table 4-6.
PAGE 53
Technical Reference Guide 4.3 ISA BUS OVERVIEW NOTE: This section describes the ISA bus in general and highlights bus implementation in this particular system. For detailed information regarding ISA bus operation, refer to the Compaq Extended Industry Standard Architecture (EISA) Technical Reference Guide. The industry standard architecture (ISA) bus provides an 8-/16-bit path for standard I/O peripherals as well as for an optional device that can be installed in the ISA expansion slot (if present).
PAGE 54
Chapter 4 System Support 4.3.1 ISA CONNECTOR 16-Bit ISA Connection 8-Bit ISA Connection D1 B1 C1 A1 NOTE: See caution below. Figure 4–6. ISA Expansion Connector Table 4–7. ISA Expansion Connector Pinout Table 4-7.
PAGE 55
Technical Reference Guide 4.3.2 ISA BUS TRANSACTIONS The ISA bus supports 8- and 16-bit transfers at an 8-MHz rate. Devices limited to 8-bit transfers use the lower byte portion (data lines 7..0) while 16-bit transfers use the full bandwidth (data lines 15..0). Addressing is handled by two classifications of address signals: latched and latchable. Latched address signals ( SA19..0) select the specific byte within the 1-MB section of memory defined by address lines LA23..17. Latchable address lines (LA23..
PAGE 56
Chapter 4 System Support The following guidelines apply to optional ISA devices installed in the system: ♦ ♦ ♦ ♦ On bus lines that can be driven by a controller board, the driver should be able to sink a minimum of 20 ma at 0.5 VDC and source 2 ma at 3.75 VDC. On bus lines that are driven in the low direction only (open collector), the driver should be able to sink 20 ma at 0.5 VDC. The load on any logic line from a single bus slot should not exceed 2.0 ma in the low state (at 0.5 VDC) or 0.
PAGE 57
Technical Reference Guide 4.3.3 DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a method by which an ISA device accesses system memory without involving the microprocessor. DMA is normally used to transfer blocks of data to or from an ISA I/O device. DMA reduces the amount of CPU interactions with memory, freeing the CPU for other processing tasks. NOTE: This section describes DMA in general.
PAGE 58
Chapter 4 System Support 4.3.3.1 Page Registers The DMA page register contains the eight most significant bits of the 24-bit address and works in conjunction with the DMA controllers to define the complete (24-bit)address for the DMA channels. Table 4-9 lists the page register port addresses. Table 4–9. DMA Page Register Addresses Table 4-9.
PAGE 59
Technical Reference Guide The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08. Address lines LA23..17, SA18,19 are driven low. The remaining address lines are in an undefined state during the refresh cycle. The refresh operations are driven by a 69.
PAGE 60
Chapter 4 System Support 4.3.4 INTERRUPTS The microprocessor uses two types of interrupts; maskable and nonmaskable. A maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor but may be inhibited by hardware or software means external to the microprocessor. 4.3.4.
PAGE 61
Technical Reference Guide Table 4–11. Maskable Interrupt Priorities and Assignments Table 4-11.
PAGE 62
Chapter 4 System Support 4.3.4.2 Non-Maskable Interrupts Non-maskble interrupts cannot be masked (inhibited) within the microprocessor itself but may be maskable by software using logic external to the microprocessor. There are two nonmaskable interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable interrupts, with the SMI- having top priority over all interrupts including the NMI-.
PAGE 63
Technical Reference Guide SMI- Generation The SMI- (System Management Interrupt) is typically used for power management functions. When power management is enabled, inactivity timers are monitored. When a timer times out, SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with the APM BIOS to service the SMI- according to the cause of the timeout.
PAGE 64
Chapter 4 System Support 4.3.5 INTERVAL TIMER The interval timer generates pulses at software (programmable) intervals. A 8254-compatible timer is integrated into the South Bridge chip. The timer function provides three counters, the functions of which are listed in Table 4-13. Table 4–13. Interval Timer Functions Table 4-13. Interval Timer Functions Counter 0 1 2 Function System Clock Refresh Speaker Tone Gate Always on Always on Port 61, bit<0> Clock In 1.193 MHz 1.193 MHz 1.
PAGE 65
Technical Reference Guide 4.4 SYSTEM CLOCK DISTRIBUTION The system uses an ICS9147-08 or compatible part for generation of most clock signals. Tables 4-15 lists the clock signals and to which components they are distributed. Table 4–15. Clock Generation and Distribution (Pentium-Based System) Table 4-15.
PAGE 66
Chapter 4 System Support 4.5 REAL-TIME CLOCK AND CONFIGURATION MEMORY The Real-time clock (RTC) and configuration memory functions are provided by the PC87307 I/O controller. The RTC uses the first 14 of 256 bytes of configuration memory and is MC146818-compatible. As shown in the following figure, the 87307 controller provides 256 bytes of configuration memory, divided into two 128-byte banks.
PAGE 67
Technical Reference Guide 4.5.1 CONFIGURATION MEMORY BYTE DEFINITIONS Table 4-16 lists the mapping of the configuration memory. Table 4–16. Configuration Memory (CMOS) Map Table 4-16.
PAGE 68
Chapter 4 System Support RTC Control Register A, Byte 0Ah Bit 7 6..4 3..0 Function Update in Progress. Read only. 0 = Time update will not occur before 2444 us 1 = Time update will occur within 2444 us Divider Chain Control. R/W. 00x = Oscillator disabled. 010 = Normal operation (time base frequency = 32.768 KHz). 11x = Divider chain reset. Periodic Interrupt Control. R/W. Specifies the periodic interrupt interval. 0000 = none 1000 = 3.90625 ms 0001 = 3.90625 ms 1001 = 7.8125 ms 0010 = 7.
PAGE 69
Technical Reference Guide Configuration Byte 0Eh, Diagnostic Status Default Value = 00h This byte contains diagnostic status data. Configuration Byte 0Fh, System Reset Code Default Value = 00h This byte contains the system reset code. Configuration Byte 10h, Diskette Drive Type Bit Function 7..4 Primary (Drive A) Diskette Drive Type 3..0 Secondary (Drive B) Diskette Drive Type Valid values for bits <7..4> and bits <3..0>: 0000 = Not installed 0001 = 360-KB drive 0010 = 1.
PAGE 70
Chapter 4 System Support Configuration Byte 13h, Security Functions Default Value = 00h Bit Function 7 Reserved 6 QuickBlank Enable After Standby: 0 = Disable 1 = Enable 5 Administrator Password: 0 = Not present 1 = Present 4 Reserved 3 Diskette Boot Enable: 0 = Enable 1 = Disable 2 QuickLock Enable: 0 = Disable 1 = Enable 1 Network Server Mode/Security Lock Override: 0 = Disable 1 = Enable 0 Password State (Set by BIOS at Power-up) 0 = Not set 1 = Set Configuration Byte 14h, Equipment Installed Default V
PAGE 71
Technical Reference Guide Configuration Bytes 19h-1Ch, Hard Drive Types Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4> hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte 12h bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and 2 of the secondary controller.
PAGE 72
Chapter 4 System Support Configuration Byte 26h, Auxiliary Peripheral Configuration Default Value = 00h Bit Function 7,6 I/O Delay Select 00 = 420 ns (default) 01 = 300 ns 10 = 2600 ns 11 = 540 ns 5 Alternative A20 Switching 0 = Disable port 92 mode 1 = Enable port 92 mode 4 Bi-directional Print Port Mode 0 = Disabled 1 = Enabled 3 Graphics Type 0 = Color 1 = Monochrome 2 Hard Drive Primary/Secondary Address Select: 0 = Primary 1 = Secondary 1 Diskette I/O Port 0 = Primary 1 = Secondary 0 Diskette I/O Port
PAGE 73
Technical Reference Guide Default Value = 00h Bit Function 7..5 Reserved 4 Primary Hard Drive Enable (Non-PCI IDE Controllers) 0 = Disable 1 = Enable 3..0 Reserved Configuration Byte 2Ah, Hard Drive Timeout Default Value = 02h Bit Function 7..5 Reserved 4..0 Hard Drive Timeout 00000 = Disabled 00001 = 1 minute 00010 = 2 minutes . .
PAGE 74
Chapter 4 System Support Configuration Byte 2Dh, Additional Flags Default Value = 00h Bit Function 7..5 Reserved 4 Memory Test 0 = Test memory on power up only 1 = Test memory on warm boot 3 POST Error Handling (BIOS Defined) 0 = Display “Press F1 to Continue” on error 1 = Skip F1 message 2..0 Reserved Configuration Byte 2Eh, 2Fh, Checksum These bytes hold the checksum of bytes 10h to 2Dh.
PAGE 75
Technical Reference Guide Configuration Byte 35h, APM Status Flags Default Value = 11h Bit Function 7..
PAGE 76
Chapter 4 System Support Configuration Byte 45h, Keyboard Snoop Data Default Value = xxh Bit Function 7 Cntrl/F10 Key Status: 0 = Cntrl & F10 keys not pressed 1 = Cntrl & F10 keys pressed 6 F10 Key Status: 0 = F10 key not pressed 1 = F10 key pressed 5..
PAGE 77
Technical Reference Guide Configuration Byte 52h, Board Revision This byte holds the board revision as copied from the boot block sector. Configuration Byte 53h, 54h, SW SMI Command/Data Bytes Configuration Byte 55h, APM Command Byte Configuration Byte 56h, Miscellaneous Flags Byte Bit 7 6 5 4 3..1 0 Function CAS Latency: 0 = 2, 1 = 3 IR Port Enable Flag: 0 = Disabled (COM2 config. for standard serial port) 1 = Enabled (COM2 config.
PAGE 78
Chapter 4 System Support Configuration Byte 83h, Microprocessor Identification This byte holds the component ID and chip revision of the microprocessor. Configuration Byte 84h, Microprocessor Revision Configuration Byte 85h, Hood Lock/Administration Mode Bit 7,6 5 4 3 2 1 0 Function Reserved ESCD Buffering: 0 = No buffering, 1 = ESCD buffered at F000h.
PAGE 79
Technical Reference Guide Configuration Byte 90h, 91h, Total Super Extended Memory Configured This byte holds the value of the amount of extended system memory that is configured. The amount is given in 64-KB increments. Configuration Byte 92h, Miscellaneous Configuration Byte Default Value = 18h Bit Function 7..5 Reserved 4 Diskette Write Control: 0 = Disable 1 = Enable 3..
PAGE 80
Chapter 4 System Support Configuration Byte 94h, ROM Flash/Power Button Status Default Value = 00h Bit Function 7..5 Reserved 4 ROM Flash In Progress (if set) 3 Reserved 2 Power Button Inhibited (ifset) 1 User-Forced Bootblock (if set) 0 ROM Flash In Progress (if set) Configuration Byte 97h, Asset/Test Prompt Byte Default Value = 00h Bit Function 7,6 Test Prompt: 01 = Fake F1 10 = Fake F2 11 = Fake F10 5..0 Asset Value Configuration Byte 9Bh, Ultra-33 DMA Enable Byte Default Value = 00h Bit Function 7..
PAGE 81
Technical Reference Guide Configuration Byte 9Dh, ESS Audio Configuration Byte Default Value = 12h Bit Function 7 Reserved for Game Port Enable 6,5 Audio Address 00 = 22xh 01 = 23xh 10 = 24xh 11 = 25xh 4,3 DMA Channel 00 = Disabled 01 = DMA0 10 = DMA1 11 = DMA3 2,1 IRQ Select 00 = IRQ9 01 = IRQ5 10 = IRQ7 11 = IRQ10 0 ESS Audio Chip Enable 0 = Enabled 1 = Disabled Configuration Byte 9Eh, ECP DMA Configuration Byte Default Value = 03h Bit Function 7..
PAGE 82
Chapter 4 System Support Configuration Byte C7h, C8h, Serial Ports 1 and 2 (Respectively) Configuration Bytes Default Value = FEh, 7Dh Bit Function 7..2 Base I/O Address (in packed format) (Algorithm: [Addr. - 200h] / 8) (i.e., 3Fh = 3F8h, 1Fh = 2F8h, 00 = 200h) 1..
PAGE 83
Technical Reference Guide 4.6 I/O MAP AND REGISTER ACCESSING This section describes the system I/O map and methods of accessing various system functions. 4.6.1 SYSTEM I/O MAP Table 4–17. System I/O Map Table 4-17. System I/O Map I/O Port Function 0000..000Fh DMA Controller 1 0020..0021h Interrupt Controller 1 0040..0043h Timer 1 0060h Keyboard Controller Data Byte 0061h NMI, Speaker Control 0064h Keyboard Controller Command/Status Byte 0070h NMI Enable, RTC Address 0071h RTC Data 0078h..
PAGE 84
Chapter 4 System Support 4.6.2 87307 I/O CONTROLLER CONFIGURATION The 87307 I/O controller contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. Software control of these interfaces uses standard AT-type I/O addressing. Firmware configuration of these functions uses indexed ports unique to the 87307.
PAGE 85
Technical Reference Guide The 87307 I/O Controller provides 11 general purpose pins that can be individually configured as either inputs or outputs. These pins are mapped as two general purpose ports and softwareaccessable through the registers shown below. GPIO Port 1 Data, I/O Addr. 078h, (87307 I/O Controller) Bit 7..4 3 2 1,0 Function GPIO17..GPIO14: Not used. GPIO13 (config. as input). Bus Fraction (BF2) GPIO12 (config. as input): CPU Bus Speed Read 0, 60 MHz Read 1, 66 MHz GPIO11,10 (config.
PAGE 86
Chapter 4 System Support 4.7 SYSTEM MANAGEMENT SUPPORT This section describes the hardware support of functions involving security, safety, identification, and power consumption of the system. System management functions are handled largely through a Compaq-proprietary ASIC. Most functions are controlled through registers (Table 419) accessed using the indexed method through I/O ports 0C50h (index) and 0C51h (Data). Table 4–19. System Management Control Registers Table 4-19.
PAGE 87
Technical Reference Guide 4.7.2 PASSWORD PROTECTION When enabled, the user is prompted to enter the power-on password during POST. If an incorrect entry is made, the system halts and does not boot. The Power-On password is stored in eight bytes at configuration memory locations 37h-3Fh. These locations are physically located within the 87307. At the time a new password is written into 37h-3Fh, the password is also written into Black Box* logic.
PAGE 88
Chapter 4 System Support 4.7.3 I/O SECURITY The 87307 I/O controller allows various I/O functions to be disabled through configuration registers.
PAGE 89
Technical Reference Guide 4.7.5 TEMPERATURE SENSING Two components (one programmable LM75 and one TC623) are used in monitoring the internal temperature of the system. The LM75 sensor is mounted in the cavity of the microprocessor socket to detect microprocessor temperature. The LM75 is programmed for two temperature levels: a. Tos - Overtemperature shutdown value (level at which the LM75’s output becomes active) b.
PAGE 90
Chapter 4 System Support 4.7.6 POWER MANAGEMENT This system includes hardware support of Advanced Power Management (APM ver. 1.2) firmware and software and is Energy Star-compliant. 4.7.6.1 HARD DRIVE SPINDOWN CONTROL The timeout parameter stored in the SIT record 04h and indexed through CMOS location 2Ah (bits <4..0>) represents the period of hard drive inactivity required to elapse before the hard drive is allowed to spin down. The timeout value is downloaded from CMOS to a timer on the hard drive.
PAGE 91
Technical Reference Guide Chapter 5 INPUT/OUTPUT INTERFACES 5. 5.1 Chapter 5 INPUT/OUTPUT INTERFACES INTRODUCTION This chapter describes the system’s interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The I/O interfaces are integrated functions of the support chipset and the 87307 I/O controller. The following I/O interfaces are covered in this chapter: ♦ ♦ ♦ ♦ ♦ ♦ ♦ 5.2 Enhanced IDE (EIDE) interface (5.
PAGE 92
Chapter 5 Input/Output Interfaces 5.2.1.1 IDE Configuration Registers The IDE interface is handled by the 82586 component and configured as a PCI device with bus mastering capability. The PCI configuration registers for the IDE controller function (PCI device #20, function #1) are listed in Table 5-1. Table 5–1. IDE PCI Configuration Registers Table 5-1. EIDE PCI Configuration Registers (82586, Function 1) PCI Conf. Addr.
PAGE 93
Technical Reference Guide 5.2.1.3 IDE ATA Control Registers The IDE controller of the 82586 decodes the addressing of the standard AT attachment (ATA) registers for the connected drive, which is where the ATA control registers actually reside. The primary and secondary interface connectors are mapped as shown in Table 5-3. Table 5–3. IDE ATA Control Registers Table 5-3. IDE ATA Control Registers Primary I/O Addr. 1F0h 1F1h 1F1h 1F2h 1F3h 1F4h 1F5h 1F6h 1F7h 1F7h 3F6h 3F6h 3F7h 3F7h Secondary I/O Addr.
PAGE 94
Chapter 5 Input/Output Interfaces The contents of the Error register are interpreted as a diagnostic status byte after the execution of a diagnostic command or when the system is initialized.
PAGE 95
Technical Reference Guide Drive Select/Head Register, I/O Port 1F6h/176h Bit 7 6,5 4 3..
PAGE 96
Chapter 5 Input/Output Interfaces Command Register, I/O Port 1F7h/177h (Write Only) The IDE controller commands are written to this register. The command write action should be prefaced with the loading of data into the appropriate registers. Execution begins when the command is written to 1F7h/177h. Table 5-4 lists the standard IDE commands. Table 5–4. IDE Controller Commands Table 5-4.
PAGE 97
Technical Reference Guide Drive Control Register, I/O Port 3F6h/376h (Write Only) Bit 7..3 2 1 0 Function Reserved Controller Control: 0 = Re-enable 1 = Reset Interrupt Enable/Disable 0 = Disable interrupts 1 = Enable interrupts Reserved Drive Access Register, I/O Port 3F7h/377h (Read Only) Bit 7 6 5..
PAGE 98
Chapter 5 Input/Output Interfaces 5.2.2 IDE CONNECTORS This system includes two standard 40-pin connectors and one 50-pin connector for IDE devices. Devices attached to the 40-pin connectors obtain power through a separate connector. The 40-pin connector is shown in the illustration below followed by the connector’s pinout. Figure 5–1. 40-Pin IDE Connector. Table 5–5. 40-Pin IDE Connector Pinout Table 5-5.
PAGE 99
Technical Reference Guide The 50-pin connector is intended for a CD-ROM drive that operates as a slave on the secondary IDE interface. This interface includes power and audio signals. The 50-pin connector is illustrated below followed by the pinout. P2 P50 P1 P49 Figure 5–1. 50-Pin IDE Connector. Table 5–6. 40-Pin IDE Connector Pinout Table 5-5.
PAGE 100
Chapter 5 Input/Output Interfaces 5.3 DISKETTE DRIVE INTERFACE The diskette drive interface supports up to two diskette drives through a standard 34-pin diskette drive connector. All Deskpro 4000S models include a 3.5 inch 1.44-MB diskette drive installed as drive A. There is no physical provision for a second drive (B). The diskette drive interface function is integrated into the 87307 I/O controller component.
PAGE 101
Technical Reference Guide 5.3.1 DISKETTE DRIVE PROGRAMMING 5.3.1.1 Diskette Drive Interface Configuration The diskette drive controller must be configured for a specific address and also must be enabled before it can be used. Address selection and enabling of the diskette drive interface are affected by firmware through the PnP configuration registers of the 87307 I/O controller. The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh (data).
PAGE 102
Chapter 5 Input/Output Interfaces 5.3.1.2 Diskette Drive Interface Control The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette drive interface can be controlled by software through I/O-mapped registers listed in Table 5-7. Table 5–8. Diskette Drive Controller Registers Table 5-7.
PAGE 103
Technical Reference Guide Main Status Register, I/O Port 3F4h/374h (Read Only) Bit 7 6 5 4 3..0 Function Request for Master. When set, indicates the controller is ready to send or receive data from the CPU. Cleared immediately after a byte transfer. Indicates interrupt pin status during nonDMA phase. Data I/O Direction. 0 = Expecting a write 1 = Expecting a read Non-DMA Execution. When set, indicates controller is in the execution phase of a byte transfer in non-DMA mode. Command In Progress.
PAGE 104
Chapter 5 Input/Output Interfaces 5.3.2 DISKETTE DRIVE CONNECTOR This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-8 for the pinout) for diskette drives. Drive power is supplied through a separate connector. 2 4 1 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Figure 5–2. 34-Pin Diskette Drive Connector. Table 5–9. 34-Pin Diskette Drive Connector Pinout Table 5-8.
PAGE 105
Technical Reference Guide 5.4 SERIAL INTERFACES The serial interfaces transmit and receive asynchronous serial data with external devices. The serial interface function is provided by the 87307 I/O controller component, which integrates two 16550/16450-compatible UARTs. One UART(1) is dedicated to support DB-9 connector (A) on the rear of the chassis while the second UART(2) can be configured to support the second DB-9 connector (B). 87307 UART1 (Log. Dev.
PAGE 106
Chapter 5 Input/Output Interfaces 5.4.2 SERIAL INTERFACE PROGRAMMING 5.4.2.1 Serial Interface Configuration The serial interfaces must be configured for a specific address range (COM1, COM2, etc.) and also must be activated before it can be used. Address selection and activation of the serial interface are affected through the PnP configuration registers of the 87307 I/O controller. The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh (data).
PAGE 107
Technical Reference Guide 5.4.2.2 Serial Interface Control The BIOS function INT 14 provides basic control of the serial interface. The serial interface can be controlled by software through the registers listed in Table 5-12. Table 5–12. Serial Interface Control Registers Table 5-12.
PAGE 108
Chapter 5 Input/Output Interfaces Baud Rate Divisor Latch Register, I/O Port 3F8h, 3F9h/2F8, 2F9h When bit <7> of the Line Control register is set (1), a write to this pair of locations loads the decimal value used to divide the 1.8462-MHz clock to create the desired baud rate for serial transmission. The possible baud rates are shown as follows: Baud Rate 50 75 110 134.
PAGE 109
Technical Reference Guide FIFO Control Register, I/O Port 3FAh/2FAh (Write Only) This write-only register enables and clears the FIFOs and set the trigger level and DMA mode. Bit 7,6 5..3 2 1 0 Function Receiver Trigger Level 00 = 1 byte 10 = 8 bytes 01 = 4 bytes 11 = 14 bytes Reserved Transmit FIFO Reset (if set) Receive FIFO Reset (if set) FIFOs Enable/Disable 0 = Disable TX/RX FIFOs, 1 = Enable TX/RX FIFOs Line Control Register, I/O Port 3FBh/2FBh This register specifies the data transmission format.
PAGE 110
Chapter 5 Input/Output Interfaces Line Status Register, I/O Port 3FDh/2FDh (Read Only) This register contains the status of the current data transfer. Bits <2..0> are cleared when read. Bit 7 6 5 4 3 2 1 0 Function Parity Error, Framing Error, or Break Cond. Exists (if set) TX Holding Reg. and Transmitter Shift Reg. Are Empty (if set) TX Holding Reg.
PAGE 111
Technical Reference Guide 5.5 PARALLEL INTERFACE The parallel interface provides connection to a peripheral device that has a compatible interface, the most common being a printer. The parallel interface function is integrated into the 87307 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device.
PAGE 112
Chapter 5 Input/Output Interfaces 5.5.2 ENHANCED PARALLEL PORT MODE In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If compatible, then EPP mode can be used.
PAGE 113
Technical Reference Guide 5.5.4 PARALLEL INTERFACE PROGRAMMING 5.5.4.1 Parallel Interface Configuration The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also must be enabled before it can be used. When configured for EPP or ECP mode, additional considerations must be taken into account. Address selection, enabling, and EPP/ECP mode parameters of the parallel interface are affected through the PnP configuration registers of the 87307 I/O controller.
PAGE 114
Chapter 5 Input/Output Interfaces 5.5.4.2 Parallel Interface Control The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17. The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP).
PAGE 115
Technical Reference Guide Status Register, I/O Port 379h, Read Only This register contains the current printer status. Reading this register clears the interrupt condition of the parallel port.
PAGE 116
Chapter 5 Input/Output Interfaces FIFO Register, I/O Port 7F8h (ECP Mode Only) While in ECP/forward mode, this location is used for filling the 16-byte FIFO with data bytes. Reads have no effect (except when used in Test mode). While in ECP/backward mode, reads yield data bytes from the FIFO. Configuration Register A, I/O Port 7F8h (ECP Mode Only) A read of this location yields 10h, while writes have no effect.
PAGE 117
Technical Reference Guide 5.5.5 PARALLEL INTERFACE CONNECTOR Figure 5-4 and Table 5-15 show the connector and pinout of the parallel inrteface connector. Figure 5–5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis) Table 5–15. DB-25 Parallel Connector Pinout Table 5-15.
PAGE 118
Chapter 5 Input/Output Interfaces 5.6 KEYBOARD/POINTING DEVICE INTERFACE The keyboard/pointing device interface provides the connection of an enhanced keyboard and a mouse using PS/2-type connections. The keyboard/pointing device interface function is provided by the 87307 I/O controller component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing device using bi-directional serial data transfers.
PAGE 119
Technical Reference Guide Control of the data and clock signals is shared by the 8042and the keyboard depending on the originator of the transferred data. Note that the clock signal is always generated by the keyboard. After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a parity error or timeout occurs, a Resend command is sent to the 8042. Table 5-16 lists and describes commands that can be issued by the 8042 to the keyboard. Table 5–16.
PAGE 120
Chapter 5 Input/Output Interfaces 5.6.2 POINTING DEVICE INTERFACE OPERATION The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical to the keyboard connector both physically and electrically. The operation of the interface (clock and data signal control) is the same as for the keyboard. The pointing device interface uses the IRQ12 interrupt. 5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING 5.6.3.
PAGE 121
Technical Reference Guide 5.6.3.2 8042 Control The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Subfunctions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the keyboard’s scan codes into ASCII codes).
PAGE 122
Chapter 5 Input/Output Interfaces Table 5-18 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for gaining the attention of the CPU. Table 5–18. CPU Commands To The 8042 Table 5-18. CPU Commands To The 8042 Value 20h 60h A4h A5h A6h A7h A8h A9h AAh ABh ADh AEh Command Description Put current command byte in port 60h. Load new command byte. This is a two-byte operation described as follows: 1. Write 60h to port 64h. 2.
PAGE 123
Technical Reference Guide Table 5-18. CPU Commands To The 8042 (Continued) Value C0h C2h C3h D0h D1h D2h D3h D4h E0h F0hFFh Command Description Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port to the output buffer so that they can be read at port 60h.
PAGE 124
Chapter 5 Input/Output Interfaces 5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR There are separate connectors for the keyboard and pointing device. Both connectors are identical both physically and electrically. Figure 5-6 and Table 5-19 show the connector and pinout of the keyboard/pointing device interface connectors. Figure 5–7. Keyboard or Pointing Device Interface Connector (as viewed from rear of chassis) Table 5–19. Keyboard/Pointing Device Connector Pinout Table 5-19.
PAGE 125
Technical Reference Guide 5.7 ETHERNET INTERFACE The system board integrates an Ethernet interface that supports both 10 and 100 Mbps Ethernet communications using IEEE 802.3 (ISO 8802-3) protocol. Two connection options are available; an RJ-45 jack for twisted-pair Ethernet (TPE) systems (10BaseT and 100BaseTX) and an AUI connector for a direct 10BaseT connection or to a 10Base2 connection through and AUI-to-BNC adapter. The Ethernet interface (Figure 5-9) is based on the Texas Instruments TLAN3.
PAGE 126
Chapter 5 Input/Output Interfaces 5.7.1 NIC CONFIGURATION/CONTROL The NIC is a PCI device and configured through PCI configuration space registers. The NIC is controlled through I/O registers mapped in the 300h-30Fh range. 5.7.2 NIC CONNECTORS The network interface provides two choices of connection to a LAN system as shown in the following figures. 1 15 Pin 1 2 3 4 5 6 7 8 Description Ground Control In TX Data Ground RX Data Ground n/c Ground Figure 5–9.
PAGE 127
Technical Reference Guide 5.8 UNIVERSAL SERIAL BUS INTERFACE The Universal Serial Bus (USB) interface provides up to 12 Mb/s data transfers between the host system and peripherals designed with a compatible USB interface. This high speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems.
PAGE 128
Chapter 5 Input/Output Interfaces 5.8.2 USB CONTROL The USB is controlled through I/O registers as listed in table 5-21. Table 5–21. USB Control Registers Table 5-21. USB Control Registers I/O Addr. 00, 01h 02, 03h 04, 05h 06, 07 08, 0B 0Ch 10, 11h 12, 13h 5.8.3 Register Command Status Interupt Enable Frame No. Frame List Base Address Start of Frame Modify Port 1 Status/Control Port 2 Status/Control USB CONNECTOR The USB interface provides two connectors. 1 2 3 4 Figure 5–11.
PAGE 129
Technical Reference Guide Chapter 6 GRAPHICS SUBSYSTEM 6. Chapter 6 GRAPHICS SUBSYSTEM 6.1 INTRODUCTION This chapter describes the graphics subsystem. The graphics subsystem is integrated onto the system board and operates as a PCI peripheral device. Topics covered in this chapter include: ♦ ♦ Subsystem overview (6.2) S3 Trio64V2/GX-based subsystem (6.3) page 6-1 page 6-2 Table 6-1 provides an overview of the graphics subsystem. Table 6–1. Graphics Subsystem Comparison Table 6-1.
PAGE 130
Chapter 6 Graphics Subsystem 6.2 SUBSYSTEM DESCRIPTION The graphics subsystem consists of the S3 Trio64V2/GX graphics controller and two megabytes of SGRAM for the frame buffer memory. The graphics BIOS code is included in the system BIOS ROM. This subsystem provides full multimedia support (with software MPEG acceleration) for a maximum resolution of 1024x768 with 256 colors @ 85 Hz, non-interlaced. 2-MB SGRAM Processor/ Memory Subsystems Graphics Memory Bus (63..
PAGE 131
Technical Reference Guide 6.2.2 S3 TRIO64V2/GX GRAPHICS CONFIGURATIONS The Trio64V2/GX-based graphics subsystem directly supports standard CGA, EGA, and VGA modes. Using the supplied drivers, the controller with this system supports the extended VGA modes listed in the table below. All modes are supported by the Win NT3.51 and 4.0, Win 3.1 and 95, and OS/2 operating systems unless otherwise noted. Table 6–2. S3 Trio64V2/GX-Based Subsystem Extended VGA Modes Table 6-2.
PAGE 132
Chapter 6 Graphics Subsystem 6.2.3 S3 TRIO64V2/GX GRAPHICS SUBSYSTEM PROGRAMMING The S3 Trio64V2/GX is compatible with software written for VGA, EGA, and CGA modes. Drivers are supplied for control of graphics (GUI) accelerator engines used in extended VGA modes. 6.2.3.1 Subsystem Configuration The graphics subsystem works off the PCI bus and is configured through the Trio64V2’s PCI configuration space registers (listed in Table 6-3) using PCI protocol.
PAGE 133
Technical Reference Guide Table 6–5. S3-Specific Control Register Mapping Table 6-5. S3-Specific Control Register Mapping I/O Address Function 3x5.2D..3Ch [1] Extended VGA Registers 3x5.40..4Fh [1] Control Registers 3x5.50..6Fh [1] Extension Registers --x = B, Monochrome x = C, Color [1] Index at 3x4h [2] Addresses not contiguously used through range. 6.2.
PAGE 134
Chapter 6 Graphics Subsystem 6.2.5 CONNECTORS The graphics subsystem provides a VGA monitor connector described in the following figure and table. Figure 6–2. VGA Monitor Connector, (Female DB-15, as viewed from the rear of chassis). Table 6–7. DB-15 Monitor Connector Pinout Table 6-7.
PAGE 135
Technical Reference Guide Chapter 7 POWER and SIGNAL DISTRIBUTION 7. Chapter 7 POWER SUPPLY AND DISTRIBUTION 7.1 INTRODUCTION This chapter describes the power supply and method of general power and signal distribution in the Compaq Deskpro 4000N and 4000S Personal Computers. All models use a 76-watt power supply assembly. Power distribution is basically similar in all models. Topics covered in this chapter include: ♦ ♦ ♦ 7.2 Power supply assembly/control (7.2) Power distribution (7.
PAGE 136
Chapter 7 Power and Signal Distribution 7.2.1 POWER SUPPLY ASSEMBLY The 76-watt power supply assembly is contained in a single unit that features a selectable input voltage of 90-132 VAC and 180-264 VAC. The power supply assembly provides +3.5 VDC, +5 VDC, -5 VDC, +12 VDC, and -12 VDC potentials for the system board, expansion board(s), and installed drives. These voltages are controlled by the PS On signal from the Power Control Logic.
PAGE 137
Technical Reference Guide 7.2.2 POWER CONTROL The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted (high), the Power Supply Assembly is activated. When PS On is de-asserted, the Power Supply Assembly (and the rest of the system) is off. The PS On signal is typically controlled through the Power Button, which can be set by software (Windows 95) to operate as either a standard On/Off button or as a Suspend button.
PAGE 138
Chapter 7 Power and Signal Distribution 7.3 POWER DISTRIBUTION 7.3.1 3.5/5/12 VDC DISTRIBUTION The power supply assembly includes a connector (P1) that mates directly with the system board connector (P17) when the assembly is installed. The power supply assembly also includes a cable assembly that routes +3.5 VDC, +5 VDC, -5 VDC, +12 VC, and -12 VDC to the individual drive assemblies.
PAGE 139
Technical Reference Guide 7.3.2 LOW VOLTAGE DISTRIBUTION The system board includes a provision for producing 2.5 VDC for microprocessors that require such a level for core power. The low voltage circuitry (Figure 7-3) consists of a power MOSFET and regulator components that produce 2.8 VDC, plus or minus 3.57%. 2SK1388 +3.3 VDC +2.8 VDC Microprocessor Power Supply Assembly Regulator Circuit +12 VDC 2.5 V Proc. Detect Microprocessor Figure 7–3.
PAGE 140
Chapter 7 Power and Signal Distribution 7.4 SIGNAL DISTRIBUTION Figure 7-4 shows general signal distribution between the main subassemblies of the system unit. 32-Bit PCI Bus PCI Connector Riser Card Conn J4 Riser Card 16-Bit ISA Bus HD Activity ISA Connector [1] P16 System Board SW/LED Conn Power P17 Conn P20 IDE Conn PWR SW, PWR LED, HD LED +3.5, +/- 5, +/- 12 VDC [2] Power Supply Assembly IDE I/F IDE Hard Drive IDE P21 Conn IDE I/F CD-ROM Dsk.
PAGE 141
Technical Reference Guide Chapter 8 BIOS ROM 8. Chapter 8 BIOS ROM 8.1 INTRODUCTION The Basic Input/Output System (BIOS) of the computer is a collection of machine language programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power management activities, and Setup. This chapter includes the following topics: ♦ ♦ ♦ ♦ ♦ Boot Functions (8.2) Accessing configuration memory (8.
PAGE 142
Chapter 8 BIOS ROM 8.2 BOOT FUNCTIONS The system supports new system boot functions to support remote ROM flashing and PC97 requirements. This system also supports the EL Torito specification for bootable CDs. NOTE: This system will not boot CDs intended for use in Compaq ProLiant and ProSignia products. 8.2.1 BOOT BLOCK This system includes 24 KB of boot block ROM that provides a way to recover from a failed remote flashing of the system BIOS ROM.
PAGE 143
Technical Reference Guide 8.3 ACCESSING CONFIGURATION MEMORY Configuration memory (CMOS and NVRAM) should be accessed using the appropriate BIOS function. The following subsections describe several BIOS functions available to applications for accessing the system’s non-volatile memory. 8.3.1 ACCESSING CMOS For accessing CMOS bytes, the calling application should use INT 15 AX=E823h, which is described as follows: INPUT: EAX BH BL CX OUTPUT: (Successful) CF AH AL (Failure) CF AH 8.3.
PAGE 144
Chapter 8 BIOS ROM 8.3.2.1 INT 15, AX=E841h, BL=00h - Set CMOS Defaults This function sets a bit in NVRAM that instructs the BIOS to load NVRAM with default values during the next system boot. The user will not be prompted when the default values are set. Note that the ESCD area of NVRAM is not affected by this function. Any required changes to the ESCD area must be made by the calling application invoking PnP BIOS functions.
PAGE 145
Technical Reference Guide 8.4 CLIENT MANAGEMENT SUPPORT Client Management deals with issues of security, identification, and system management functions. A group of BIOS INT 15 functions are provided to support Client Management. These functions are listed Table 8-2. Table 8–1. PnP Client Management Functions (INT15) Table 8-2.
PAGE 146
Chapter 8 BIOS ROM To support Windows NT an additional table to the BIOS32 table has been defined to contain 32bit pointers for the DDC and SIT locations.
PAGE 147
Technical Reference Guide 8.4.1 SYSTEM ID The INT 15, AX=E800h BIOS function can be used by software to identify the system. The system ID will be returned in the BX register as follows: Series Deskpro 4000N Deskpro 4000S 8.4.2 System ID 03D8h 038Ch SYSTEM INFORMATION TABLE The System Information Table (SIT) is a comprehensive list of fixed configuration information arranged into records.
PAGE 148
Chapter 8 BIOS ROM Timeout Counter Record (Video Screensave), SIT Record 03h Byte [1] Function 0Ah Record ID for Video Screensave Timeout 0Bh No. of Data Bytes in Record 0Ch First Value 0Dh 0Eh 0Fh 10h 11h 12h 13h 14H Last Value NOTE: [1] Offset from byte 00h of timeout record 02h. Default Value 03h 09h 0 5 10 15 20 30 40 50 60 Timeout Counter Record (Hard Drive), SIT Record 04h Byte [1] Function 15h Record ID for Hard Drive Timeout 16h No.
PAGE 149
Technical Reference Guide Peripheral and Input Device Record, SIT Record 07h Byte 00h 01h 02h 03h 04h 05h 06h 07h-0Ah 0Bh 0Ch 0Dh 0Eh 0Fh, 10h 11h, 12h 13h 14h, 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch, 1Dh 1Eh, 1Fh 20h, 21h 22h, 23h 24h 25h 26h 27h 28h-2Bh 2Ch-2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h Function Record ID No. of Data Bytes in Record DMA Functions, SCSI Support, Flashable ROM, Setup Partition, 101 Keyboard Erase-Eaze Kybd.
PAGE 150
Chapter 8 BIOS ROM Memory Module Information Record, SIT Record 08h Byte Function 00h Record ID 01h No. of Data Bytes in Record 02h No.
PAGE 151
Technical Reference Guide Extended Disk Support Record, SIT Record 0Eh Default Value 0Eh 02h [1] [1] Byte Function 00h Record ID 01h No. of Data Bytes in Record 02h Pointer To Extended Disk table (High Byte) 03h Pointer To Extended Disk table (Low Byte) NOTE: [1] Determined at runtime. System Record, SIT Record 0Fh (Not Used) Product Name Header Record, SIT Record 10h Byte 00h 01h 02h-14 15h Function Record ID No.
PAGE 152
Chapter 8 BIOS ROM 8.4.3 TEMPERATURE SENSOR A temperature sensor component is mounted in the cavity of the microprocessor socket. This sensor component detects when the microprocessor has reached a programmed temperature level and initiates appropriate action. The sensor is programmed by BIOS for two temperature levels; a level for initiating a caution to the user and another level to initiate a system shutdown.
PAGE 153
Technical Reference Guide 8.4.5 DIMM SUPPORT The BIOS includes DIMM support consisting of the following: ♦ ♦ ♦ Access control with the serial (I2C) EEPROM of the DIMM Runtime information on ECC-correctable single bit errors POST message if ECC-correctable errors are detectable during POST memory test DIMMs with 128 bytes of EEPROM can be used although 256-byte EEPROM DIMMs are recommended for full support of Compaq intelligent manageability features.
PAGE 154
Chapter 8 BIOS ROM ENTRY: AX = BH = E827h 02h RETURN: CF = 0 (Success) AH = 0 0000h (if no single bit ECC corrected error has occurred) bit <0>, Error occurred on DIMM/SIMM pair 0 bit <1>, Error occurred on DIMM/SIMM pair 1 bit <2>, Error occurred on DIMM/SIMM pair 2 bit <3>, Error occurred on DIMM/SIMM pair 3 1 (Failure) AH = 86h (Not supported) BX = CF = The POST memory test checks for ECC-corrected single bit errors after each 64K of memory tested in a similar fashion as is done with parity.
PAGE 155
Technical Reference Guide 8.4.6 SECURITY FUNCTIONS The INT 15 AX=E829h BIOS function is used to control various security features of the system. This function may be issued remotely (over a network) by a driver. A request buffer must be built (by the driver) for each security feature prior to making the call.
PAGE 156
Chapter 8 BIOS ROM 8.4.7 ACCESSING CMOS FEATURE BITS The BIOS function INT 15, AX=E845h is a tri-modal call for accessing areas in non-volatile memory used to store variables for various features.
PAGE 157
Technical Reference Guide 8.5 PNP SUPPORT The BIOS includes Plug ’n Play (PnP) support for PnP version 1.0A. NOTE: For full PnP functionality to be realized, all peripherals used in the system must be designed as “PnP ready.” Any installed ISA peripherals that are not “PnP ready” can still be used in the system, although configuration parameters may need to be considered (and require intervention) by the user.
PAGE 158
Chapter 8 BIOS ROM 8.6 POWER MANAGEMENT SUPPORT The Compaq Deskpro 2000 system includes Advanced Power Management (APM) BIOS support that provides, if so configured, for the automatic shutdown of certain areas within a system after a specified time of inactivity has elapsed. When activity is detected, APM brings the system back up to full power to provide complete user support.
PAGE 159
Technical Reference Guide Standby - The computer is in a low power state: video is off, some subsystems may be drawing less power, and the microprocessor is halted except for servicing interrupts. Video graphics controller is under driver control and/or VSYNC is off and the power supply fan is turned off. Any of the following activities will generate a wake-up SMI and return the system to On: a. Keyboard b. Mouse c. Serial port d. Diskette drive e. Hard drive f.
PAGE 160
Chapter 8 BIOS ROM This page is intentionally blank.
PAGE 161
Technical Reference Guide Appendix A ERROR MESSAGES AND CODES A. Appendix A ERROR MESSAGES AND CODES A.1 INTRODUCTION This appendix lists the error codes and a brief description of the probable cause of the error. Note that not all errors listed in this appendix may be applicable to a particular system depending on the model and/or configuration. A.2 POWER-ON MESSAGES Table A–1. Power-On Messages Table A-1. Power-On Messages Message CMOS Time and Date Not Set (none) Run Setup A.
PAGE 162
Appendix A Error Messages and Codes A.4 POWER-ON SELF TEST (POST) MESSAGES Table A–3. Power-On Self Test (POST) Messages Table A-3.
PAGE 163
Technical Reference Guide A.5 PROCESSOR ERROR MESSAGES (1xx-xx) Table A–4. Processor Error Messages Table A-4. Processor Error Messages Message 101-01 101-02 101-91..94 102-01 102-02 102-03 102-04 102-05 102-06 102-07 102-08 102-09 102-10 102-11 102-12 102-15 102-16 102-17 102-18 102-19 102-20 102-21 103-01 103-02 103-03 104-01 104-02 104-03 105-01 105-02 105-03 105-04 105-05 105-06 105-07 Probable Cause CPU test failed 32-bit CPU test failed Multiplication test failed FPU initial sts.
PAGE 164
Appendix A Error Messages and Codes A.6 MEMORY ERROR MESSAGES (2xx-xx) Table A–5. Memory Error Messages Table A-5. Memory Error Messages Message 200-04 200-05 200-06 200-07 200-08 201-01 202-01 202-02 202-03 203-01 203-02 203-03 204-01 204-02 204-03 204-04 204-05 205-01 205-02 205-03 206-xx 210-01 210-02 210-03 211-01 211-02 211-03 213-xx 214-xx 215-xx A.
PAGE 165
Technical Reference Guide A.8 PRINTER ERROR MESSAGES (4xx-xx) Table A–7. Printer Error Messages Table A-7. Printer Error Messages Message 401-01 402-01 402-02 402-03 402-04 402-05 402-06 402-07 402-08 402-09 A.9 Probable Cause Printer failed or not connected Printer data register failed Printer control register failed Data and control registers failed Loopback test failed Loopback test and data reg. failed Loopback test and cntrl. reg. failed Loopback tst, data/cntrl. reg.
PAGE 166
Appendix A Error Messages and Codes A.10 DISKETTE DRIVE ERROR MESSAGES (6xx-xx) Table A–9. Diskette Drive Error Messages Table A-9.
PAGE 167
Technical Reference Guide A.12 MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx) Table A–11. Serial Interface Error Messages Table A-11.
PAGE 168
Appendix A Error Messages and Codes A.13 HARD DRIVE ERROR MESSAGES (17xx-xx) Table A–12. Hard Drive Error Messages Table A-12. Hard Drive Error Messages Message Probable Cause 17xx-01 Exceeded max. soft error limit 17xx-02 Exceeded max. Hard error limit 17xx-03 Previously exceeded max. soft error limit 17xx-04 Previously exceeded max.
PAGE 169
Technical Reference Guide A.14 HARD DRIVE ERROR MESSAGES (19xx-xx) Table A–13. Hard Drive Error Messages Table A-13.
PAGE 170
Appendix A Error Messages and Codes A.16 AUDIO ERROR MESSAGES (3206-xx) Table A–15. Audio Error Messages Table A-15. Audio Error Message Message 3206-xx A.17 Probable Cause Audio subsystem internal error NETWORK INTERFACE ERROR MESSAGES (60xx-xx) Table A–16. Network Interface Error Messages Table A-16.
PAGE 171
Technical Reference Guide A.18 SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx) Table A–17. SCSI Interface Error Messages Table A-17.
PAGE 172
Appendix A Error Messages and Codes A.20 CEMM PRIVILEDGED OPS ERROR MESSAGES Table A–19. CEMM Privileged Ops Error Messages Table A-19. CEMM Privileged Ops Error Messages Message 00 01 02 03 A.21 Probable Cause LGDT instruction LIDT instruction LMSW instruction LL2 instruction Message 04 05 06 07 Probable Cause LL3 instruction MOV CRx instruction MOV DRx instruction MOV TRx instruction CEMM EXCEPTION ERROR MESSAGES Table A–20. CEMM Exception Error Messages Table A-20.
PAGE 173
Technical Reference Guide Appendix B ASCII CHARACTER SET B. Appendix B ASCII CHARACTER SET B.1 INTRODUCTION This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard textmode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol.
PAGE 174
Appendix B ASCII Character Set Table B-1.
PAGE 175
Technical Reference Guide Appendix C KEYBOARD C. Appendix C KEYBOARD C.1 INTRODUCTION This appendix describes the Compaq keyboard that is included as standard with the system unit. The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions.
PAGE 176
Appendix C Keyboard C.2 KEYSTROKE PROCESSING A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power (+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms for pressed keys while at the same time monitoring communications with the keyboard interface of the system unit. When a key is pressed, a Make code is generated.
PAGE 177
Technical Reference Guide C.2.1 TRANSMISSIONS TO THE SYSTEM The keyboard processor sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system (specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and loads the data into a buffer.
PAGE 178
Appendix C Keyboard C.2.2 KEYBOARD LAYOUTS C.2.2.
PAGE 179
Technical Reference Guide C.2.2.2 Windows Enhanced Keyboards 1 18 17 39 2 3 4 5 19 20 21 22 59 8 47 46 27 48 67 66 81 80 9 26 25 65 64 93 110 24 45 44 79 78 7 23 63 62 77 76 43 42 61 60 75 92 41 40 6 94 11 28 29 50 49 68 83 82 10 95 13 31 30 51 70 69 84 12 14 15 16 32 33 34 35 36 37 52 53 54 55 56 57 72 73 74 88 89 90 71 85 87 86 96 111 112 97 98 99 100 38 58 91 101 Figure C–5. U.S.
PAGE 180
Appendix C Keyboard C.2.2.3 Windows Enhanced Keyboards w/Erase-Ease 1 18 17 39 2 3 4 5 19 20 21 22 59 93 110 45 44 8 47 46 113 27 48 67 66 81 80 9 26 25 65 64 79 78 7 24 23 63 62 77 76 43 42 61 60 75 92 41 40 6 94 11 28 29 50 49 68 83 82 10 95 13 31 30 51 70 69 84 12 14 15 16 32 33 34 35 36 37 52 53 54 55 56 57 72 73 74 88 89 90 71 85 87 86 96 111 112 97 98 99 100 38 58 91 101 Figure C–7. U.S.
PAGE 181
Technical Reference Guide C.2.3 KEYS All keys generate a make code (when pressed) and a break code (when released) with the exception of the Pause key (pos. 16), which produces a make code only. All keys, again, with the exception of the Pause key, are also typematic, although the typematic action of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the BIOS.
PAGE 182
Appendix C Keyboard C.2.3.2 Multi-Keystroke Functions Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower (normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of key positions 55-57, 72, 74, 88-90, 100, and 101. Ctrl - The Ctrl keys (pos.
PAGE 183
Technical Reference Guide C.2.3.3 Windows Keystrokes Windows-enhanced keyboards include three additional key positions. Key positions 110 and 111 (marked with the Windows logo ) have the same functionality and are used by themselves or in combination with other keys to perform specific “hot-key” type functions for the Windows operating system.
PAGE 184
Appendix C Keyboard C.2.4 KEYBOARD COMMANDS Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042type logic). Table C–1. Keyboard-to-System Commands Table C-1. Keyboard-to-System Commands Command Key Detection Error/Over/run BAT Completion BAT Failure Echo Acknowledge (ACK) Resend Keyboard ID Value 00h [1] FFh [2] AAh FCh EEh FAh FEh 83ABh Description Indicates to the system that a switch closure couldn’t be identified.
PAGE 185
Technical Reference Guide Table C–2. Keyboard Scan Codes Table C-2. Keyboard Scan Codes Key Pos.
PAGE 186
Appendix C Keyboard Table C-2.
PAGE 187
Technical Reference Guide Table C-2. Keyboard Scan Codes (Continued) Key Pos. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Legend N M , . / Shift (right) 1 2 3 Enter Ctrl (left) Alt (left) (Space) Alt (right) Ctrl (right) 98 99 100 101 102 103 104 110 0 .
PAGE 188
Appendix C Keyboard C.3 SCANNER DESCRIPTION The scanner keyboard, available as an option, integrates a scanner with a SpaceSaver Windows ’95 keyboard, providing the ability to scan hardcopy looseleaf documents for faxing or electronic storage. The scanner provides resolutions up to 400 dpi and 256 shades of gray and outputs through a standard serial interface to the system unit. Using optical character recognition (OCR) support software, printed textual data can be converted into editable files.
PAGE 189
Technical Reference Guide C.3.1 SCANNER OPERATION The scanner requires minimum user interface for normal operation. Insertion of a sheet of hardcopy activates the scanner. Operating parameters such as resolution, brightness, and motor speed are programmable for optimum performance.
PAGE 190
Appendix C Keyboard Start Scan Image (Image Aquisition) PRNU Correction MTF Correction Resolution Conversion Threshold Output Desired? Yes Threshold (Intel.) Algorithm No Gamma Conversion Halftone Output Desired? No Grayscale Compensation Yes Type of Halftone Error Diffusion Error Diffusion Algorithm Pattern Dither Pattern Dither Algorithm Packetized & Sent to Host Finish Figure C–10.
PAGE 191
Technical Reference Guide C.3.1.1 Resolution/Shade Depth The drive motor mechanism of the CIS supports a vertical resolution of 400 dpi. The CIS provides a maximum horizontal resolution of 200 dpi. These factors provide true spatial resolutions of 100 and 200 dpi. Using horizontal interpolation, pseudo 300 and 400 dpi spatial resolutions are possible. Shade depth is determined by the number of bits used to control each pixel.
PAGE 192
Appendix C Keyboard C.3.2 SCANNER INTERFACE The scanner communicates with the system unit (host) using a serial port as the primary choice of connection. The scanner interface is adaptable to several types of host connections as shown in Table C-4 (unshaded portion describes standard scanner interface with Compaq system unit). Table C–4. Scanner I/F Signals Table C-4.
PAGE 193
Technical Reference Guide C.3.2.1 Pnyb Mode In the parallel nibble or “Pnyb” mode, the scanner transfers scanned information to the system unit (host) four bits (a nibble) at a time using the P3..P0 signals, which conform to RS-232 voltage and timing specifications. The P3..P0 signals are mapped to bits <7..4> respectively of the Modem Status Register (primary address 3FEh). The nibbles are clocked into the host with each transition of the PCLK signal.
PAGE 194
Appendix C Keyboard C.3.3 SCANNER SPECIFICATIONS/REQUIREMENTS Table C–5. Scanner Specifications Table C-5. Scanner Specifications Parameter Specification [1] Dimensions (Complete keyboard unit): 20.5 in (52.07 cm) Width 2.5 in (6.35 cm) Height 9 in (22.86 cm) Depth Weight (Complete keyvoard unit) 10.1 lb (4.58 kg) Scanner Paper Sizes: Minimum 2.0 x 3.0 in (5.1 x 7.6 cm) Maximum 8.5 x 30 in 21.6 x 76.
PAGE 195
Technical Reference Guide INDEX I.
PAGE 196
Index scan codes (keyboard), C-10 scanner keyboard, C-14 SCSI adapter, 5-34 SDRAM performance times, 3-6 security features, 4-44 serial interface, 5-14 serial presence detect (SPD), 3-6 SGRAM, 6-2 signal distribution, 7-5 SilentBoot, 8-2 sockets, DIMM, 3-2 special cycles (PCI), 4-7 specifications electrical, 2-13 environmental, 2-13 physical, 2-13 power supply, 7-5 scanner (keyboard), C-20 Specifications 8x CD-ROM Drive, 2-14 Diskette Drive, 2-14, D-11 Hard Drive, 2-16 system board, 2-7 system ID, 8-7 syst