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Compaq Computer Corporation

AlphaPC 164LX Motherboard

Technical Reference Manual

Order Number: EC–R46WC–TE

Revision/Update Information:

This is a revised document. It supersedes the

AlphaPC 164LX Motherboard Technical

Reference Manual (EC–R46WB–TE).

Summary of content (124 pages)

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AlphaPC 164LX Motherboard Technical Reference Manual Order Number: EC–R46WC–TE Revision/Update Information: Compaq Computer Corporation This is a revised document. It supersedes the AlphaPC 164LX Motherboard Technical Reference Manual (EC–R46WB–TE).
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March 1999 The information in this publication is subject to change without notice. COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL ERRORS OR OMISSIONS CONTAINED HEREIN, NOR FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL.
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Contents Preface 1 Introduction 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.2 1.2.1 1.2.2 1.2.3 1.3 2 System Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21174 Core Logic Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L3 Bcache Subsystem Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.7.7 2.7.8 2.7.9 2.7.10 2.7.11 2.7.12 2.7.13 2.7.14 2.7.15 2.7.16 2.7.17 2.7.18 3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATX Hole Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Upgrading the AlphaPC 164LX 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 A 5–1 5–2 5–3 5–3 5–3 5–4 5–4 System Address Space A.1 A.2 A.3 A.3.1 A.4 A.4.1 A.5 A.6 A.7 A.7.1 A.7.2 A.8 A.8.1 A.8.2 A.9 A.10 A.11 A.12 A.13 A.14 A.15 A.15.1 A.15.2 A.16 A.16.1 A.16.2 B Configuring SDRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upgrading SDRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increasing Microprocessor Speed. . . . . .
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B.2.2 B.2.3 B.2.4 B.3 B.4 B.5 Thermal Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enclosure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alpha Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alpha Documentation . . . . . . .
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Figures 1–1 2–1 2–2 3–1 3–2 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 5–1 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 A–14 A–15 A–16 A–17 A–18 A–19 A–20 A–21 A–22 A–23 A–24 AlphaPC 164LX Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164LX Jumper/Connector/Component Location . . . . . . . . . . . . . . . . . . AlphaPC 164LX Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATX Hole Specification . . . . . . . . . .
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Tables 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 3–1 3–2 4–1 4–2 4–3 5–1 A–1 A–2 A–3 A–4 A–5 A–6 A–7 A–8 A–9 A–10 A–11 A–12 A–13 A–14 A–15 viii AlphaPC 164LX SDRAM Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . AlphaPC 164LX Jumper/Connector/Component List . . . . . . . . . . . . . . . . . . . . . . PCI Bus Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Preface Overview This manual describes the AlphaPC 164LX motherboard, a module for computing systems based on the Alpha 21164 microprocessor and the 21174 core logic chip. Audience This manual is intended for system designers and others who use the AlphaPC 164LX motherboard to design or evaluate computer systems based on the Alpha 21164 microprocessor and the 21174 core logic chip.
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• Chapter 1, Introduction, is an overview of the AlphaPC 164LX motherboard, including its components, features, and uses. • Chapter 2, System Configuration and Connectors, describes the user-environment configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations. • Chapter 3, Power and Environmental Requirements, describes the AlphaPC 164LX power and environmental requirements and provides board dimensions.
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• Binary Multiples The abbreviations K, M, and G (kilo, mega, and giga) represent binary multiples and have the following values. K M G = = = 210 (1024) 220 (1,048,576) 230 (1,073,741,824) For example: 2KB 4MB 8GB = = = 2 kilobytes = 4 megabytes = 8 gigabytes = 2 × 210 bytes 4 × 220 bytes 8 × 230 bytes Addresses Unless otherwise noted, all addresses and offsets are hexadecimal. Bit Notation Multiple-bit fields can include contiguous and noncontiguous bits contained in angle brackets (< >).
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Data Units The following data-unit terminology is used throughout this manual. Term Words Bytes Bits Other Byte Word Longword/Dword Quadword Octaword Hexword ½ 1 2 4 8 16 1 2 4 8 16 32 8 16 32 64 128 256 — — Longword 2 Longwords 2 Quadwords 2 Octawords Note Notes emphasize particularly important information. Numbering All numbers are decimal or hexadecimal unless otherwise indicated. The prefix 0x indicates a hexadecimal number.
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Signal Names All signal names are printed in boldface type. Signal names that originate in an industry-standard specification, such as PCI or IDE, are printed in the case as found in the specification (usually uppercase). Active-high signals are indicated by the _h suffix. Active-low signals have the _l suffix, a pound sign “#” appended, or a “not” overscore bar. Signals with no suffix are considered high-asserted signals. For example, signals data_h<127:0> and cia_int are active-high signals.
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– An occurrence specified as UNPREDICTABLE may or may not happen based on an arbitrary choice function. The choice function is subject to the same constraints as are UNPREDICTABLE results and must not constitute a security hole. Specifically, UNPREDICTABLE results must not depend upon, or be a function of, the contents of memory locations or registers that are inaccessible to the current process in the current access mode.
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1 Introduction This chapter provides an overview of the AlphaPC 164LX motherboard, including its components, features, and uses. The motherboard is a module for computing systems based on the 21174 core logic chip. The AlphaPC 164LX provides a single-board hardware and software development platform for the design, integration, and analysis of supporting logic and subsystems. The board also provides a platform for PCI I/O device hardware and software development. 1.
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System Components and Features Figure 1–1 AlphaPC 164LX Functional Block Diagram Index 18 Control Alpha 21164 Microprocessor 2MB L3 Bcache Bcache Tag 10 Data 128 Check 16 128-Bit Data Quick Switches (X16) 168-Pin Unbuffered SDRAM DIMM Sockets (X4) Control Address 36 DECchip 21174-CA Control, I/O Interface, and Address Commands Address/Control PCI Bus IDE Controller Support - Synthesizer - Serial ROM 2 Dedicated 64-Bit PCI Slots 2 Dedicated 32-Bit PCI Slots 2 Dedicated ISA Slots PCI-to-IS
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System Components and Features 1.1.1 21174 Core Logic Chip The Alpha 21164 microprocessor is supported by the 21174 core logic chip, which provides an interface between three units—memory, the PCI bus, and the 21164 (along with flash ROM). This core logic chip is the interface between the 21164 microprocessor, main memory (addressing and control), and the PCI bus. Sixteen quick switches provide the memory interface data path.
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System Components and Features 1.1.3 L3 Bcache Subsystem Overview The AlphaPC 164LX board-level L3 backup cache (Bcache) is a 2MB, directmapped, synchronous SRAM with a 128-bit data path. The board is capable of handling an L3 cache size of 4MB. See Section 2.3 for more information about the Bcache. 1.1.4 PCI Interface Overview The AlphaPC 164LX PCI interface is the main I/O bus for the majority of functions (SCSI interface, graphics accelerator, and so on).
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Software Support – The 21174 core logic chip provides the SDRAM and PCI clocks. – A 14.318-MHz crystal and frequency generator provide a clock source for the FDC37C935 ISA device controller. The controller’s onchip generator then provides other clocks as needed. – A 32-kHz crystal provides the TOY clock source. • Serial ROM – A Xilinx XC17128 serial ROM (SROM) contains initial code that is loaded into the 21164 instruction cache (Icache) on power-up.
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Hardware Design Support 1.2.3 Motherboard Software Developer’s Kit (SDK) The SDK is designed to provide an environment for developing software for Alpha motherboard products. It is also specially suited for low-level software development and hardware debug for other Alpha microprocessor-based designs. The following list includes some of the components of the SDK: • The Alpha Motherboard Debug Monitor firmware with source code. • Power-up initialization SROM and SROM Mini-Debugger with source code.
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2 System Configuration and Connectors This chapter describes the AlphaPC 164LX configuration, board connectors and functions, and jumper functions. It also identifies jumper and connector locations. The AlphaPC 164LX uses jumpers to implement configuration parameters such as system speed and boot parameters. These jumpers must be configured for the user’s environment. Onboard connectors are provided for the I/O interfaces, DIMMs, and serial and parallel peripheral ports.
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Figure 2–1 AlphaPC 164LX Jumper/Connector/Component Location J27 J28 J30 J31 U62 J25 J29 U61 J24 * * J26 U58 U59 U60 J23 J18 B1 * * * * * * U50 U49 U48 J17 U53 J16 * U43 J15 U42 J19 U41 U40 * * J20 J21 J22 U37 U31 U32 U33 U20 U21 U22 U8 U9 U10 J13 J5 J6 J7 J4 * * J3 J1 J8 * Denotes Pin #1 J9 J10 J11 J2 Mouse J5 Top: Bottom: Keyboard J4 Top: COM1 Bottom: COM2 FM-05933.
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Table 2–1 AlphaPC 164LX Jumper/Connector/Component List Item No. Description Item No.
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AlphaPC 164LX Configuration Jumpers 2.1 AlphaPC 164LX Configuration Jumpers The AlphaPC 164LX motherboard has two groups of jumpers located at J27 and J28, as shown previously in Figure 2–1. These jumpers set the hardware configuration and boot options. Figure 2–2 shows the jumper functions for each group.
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CPU Speed Selection 2.2 CPU Speed Selection The clock synthesizer at location U47 makes it possible to change the frequency of the microprocessor’s system clock output without having to change the clock crystal. Simply set the system clock divisor jumpers to adjust the frequency of the microprocessor’s system clock output. These system clock divisor jumpers are located at J27–1/2 (IRQ3), J27–3/4 (IRQ2), J27–5/6 (IRQ1), and J27–7/8 (IRQ0). The jumper configuration is set in IRQ3 through IRQ0.
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Flash ROM Update Jumper (J28) 2.6 Flash ROM Update Jumper (J28) When J28–2/3 are jumpered together (default), the flash ROM is write-enabled. When J28–1/2 are jumpered together, the flash ROM is write-protected. 2.7 AlphaPC 164LX Connector Pinouts This section lists the pinouts of all AlphaPC 164LX connectors. See Figure 2–1 for connector locations. 2.7.1 PCI Bus Connector Pinouts Table 2–2 shows the PCI bus connector pinouts.
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AlphaPC 164LX Connector Pinouts Table 2–2 PCI Bus Connector Pinouts (Continued) Pin Signal Pin Signal Pin Signal Pin Signal B27 B31 B35 B39 B43 B47 B51 B55 B59 AD<23> +3V IRDY# LOCK# +3V AD<12> Not used AD<05> Vdd B28 B32 B36 B40 B44 B48 B52 B56 B60 Gnd AD<17> +3V PERR# C/BE#<1> AD<10> AD<08> AD<03> ACK64# B29 B33 B37 B41 B45 B49 B53 B57 B61 AD<21> C/BE#<2> DEVSEL# +3V AD<14> Gnd AD<07> Gnd Vdd B30 B34 B38 B42 B46 B50 B54 B58 B62 AD<19> Gnd Gnd SERR# Gnd Not used +3V AD<01> Vdd A65 A69 A73
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AlphaPC 164LX Connector Pinouts 2.7.2 ISA Expansion Bus Connector Pinouts Table 2–3 shows the ISA expansion bus connector pinouts.
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AlphaPC 164LX Connector Pinouts 2.7.3 SDRAM DIMM Connector Pinouts Table 2–4 shows the SDRAM DIMM connector pinouts.
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AlphaPC 164LX Connector Pinouts Table 2–4 SDRAM DIMM Connector Pinouts (J8 through J11)1 (Continued) Pin 125 129 133 137 141 145 149 153 157 161 165 Signal CK1 S3 +3V CB7 DQ50 NC DQ53 DQ56 +3V DQ63 SA0 Pin Signal Pin Signal Pin Signal 126 130 134 138 142 146 150 154 158 162 166 BA12 127 131 135 139 143 147 151 155 159 163 167 Gnd DQMB7 NC DQ48 +3V PD DQ55 DQ58 DQ61 CK3 SA2 128 132 136 140 144 148 152 156 160 164 168 CKE0 PD3 CB6 DQ49 DQ52 Gnd Gnd DQ59 DQ62 NC +3V DQMB6 NC Gnd DQ51 NC DQ54 D
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AlphaPC 164LX Connector Pinouts 2.7.5 Diskette Drive Bus Connector Pinouts Table 2–6 shows the diskette (floppy) drive bus connector pinouts.
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AlphaPC 164LX Connector Pinouts 2.7.7 COM1/COM2 Serial Line Connector Pinouts Table 2–8 shows the COM1/COM2 serial line connector pinouts. Table 2–8 COM1/COM2 Serial Line Connector Pinouts (J4) COM1 Pin (Top) COM1 Signal COM2 Pin (Bottom) COM2 Signal 1 2 3 4 5 6 7 8 9 DCD1 RxD1 TxD1 DTR1 SG1 DSR1 RTS1 CTS1 RI1 1 2 3 4 5 6 7 8 9 DCD2 RxD2 TxD2 DTR2 SG2 DSR2 RTS2 CTS2 RI2 2.7.8 Keyboard/Mouse Connector Pinouts Table 2–9 shows the keyboard/mouse connector pinouts.
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AlphaPC 164LX Connector Pinouts 2.7.9 SROM Test Data Input Connector Pinouts Table 2–10 shows the SROM test data input connector pinouts. Table 2–10 SROM Test Data Input Connector Pinouts (J29) Pin Signal Name 1 2 3 4 5 6 NC SROM_CLK_L Gnd NC TEST_SROM_D_L NC — Clock out — — SROM serial data in — 2.7.10 Input Power Connector Pinouts Table 2–11 shows the input power connector pinouts.
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AlphaPC 164LX Connector Pinouts 2.7.12 Speaker Connector Pinouts Table 2–13 shows the speaker connector pinouts. Table 2–13 Speaker Connector Pinouts (J20) Pin Signal Name 1 2 3 4 SPKR Gnd Gnd Gnd Speaker output — — — 2.7.13 Microprocessor Fan Power Connector Pinouts Table 2–14 shows the microprocessor fan power connector pinouts. Table 2–14 Microprocessor Fan Power Connector Pinouts (J18) Pin Signal Name 1 2 3 +12V — FAN_CONN_L Fan connected Gnd — 2.7.
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AlphaPC 164LX Connector Pinouts 2.7.15 IDE Drive LED Connector Pinouts Table 2–16 shows the IDE drive LED connector pinouts. Table 2–16 IDE Drive LED Connector Pinouts (J25) Pin Signal Name 1 2 HD_ACT_L HD_LED_L Hard drive active Hard drive LED input 2.7.16 Reset Button Connector Pinouts Table 2–17 shows the reset button connector pinouts. Table 2–17 Reset Button Connector Pinouts (J21) Pin Signal Name 1 2 RESET_BUTTON Reset system Gnd — 2.7.
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3 Power and Environmental Requirements This chapter describes the AlphaPC 164LX power and environmental requirements, and physical board parameters. 3.1 Power Requirements The AlphaPC 164LX derives its main dc power from a user-supplied power supply. The board has a total power dissipation of 100 W, excluding any plug-in PCI and ISA devices. An onboard +5-V to +2.5-V dc-to-dc converter is designed to handle 24 A of current. Table 3–1 lists the power requirement for each dc supply voltage.
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Environmental Requirements 3.2 Environmental Requirements The 21164 microprocessor is cooled by a small fan blowing directly into the chip’s heat sink. The AlphaPC 164LX motherboard is designed to run efficiently by using only this fan. Additional fans may be necessary depending upon cabinetry and the requirements of plug-in cards. The AlphaPC 164LX motherboard is specified to run within the environment listed in Table 3–2.
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Board Dimensions 3.3.1 ATX Hole Specification Figure 3–1 shows the ATX hole specification for the AlphaPC 164LX. Measurements are shown in inches. Figure 3–1 ATX Hole Specification .800 TYP Between Connectors .650 .500 .400 4.900 1.612 1.300 .600 .625 8.950 PCI Connector (4 Places) 6.100 9.600 ISA Connector (2 Places) 11.100 12.000 This ATX hole is not supported on AlphaPC 164LX board, and no clearance is provided on side 2.
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Board Dimensions 3.3.2 ATX I/O Shield Requirements Figure 3–2 shows the ATX I/O shield dimensions for the AlphaPC 164LX. Measurements are shown in millimeters. 74.8 78.2 85.4 87.2 94.4 98.9 43.5 35.5 24.7 16.7 R 1.00 68.4 64.9 Figure 3–2 ATX I/O Shield Dimensions 21.36 16.05 5.00 TYP 9.25 3.58 2.45 4.35 11.15 15.47 17.95 22.95 23.96 29.10 33.10 90.17 95.40 81.18 70.39 72.19 55.05 64.04 44.26 46.06 37.91 28.92 18.13 19.93 0.99 9.98 11.78 8.00 16.15 14.35 25.14 42.28 40.48 34.13 51.
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4 Functional Description This chapter describes the functional operation of the AlphaPC 164LX. The description introduces the 21174 core logic chip and describes its implementation with the 21164 microprocessor, its supporting memory, and I/O devices. Figure 1–1 shows the AlphaPC 164LX major functional components. Bus timing and protocol information found in other data sheets and reference documentation is not duplicated. See Appendix B for a list of supporting documents and order numbers.
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AlphaPC 164LX Bcache Interface 4.1 AlphaPC 164LX Bcache Interface The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array (see Figure 4–1). The data bus (data_h<127:0>), check bus (data_check_h<15:0>), tag_dirty_h, and tag_ctl_par_h signals are shared with the system interface.
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21174 Core Logic Chip 4.2 21174 Core Logic Chip The 21174 core logic chip provides a cost-competitive solution for designers using the 21164 microprocessor to develop uniprocessor systems. The chip provides a 128-bit memory interface and a PCI I/O interface, and includes the 21174-CA chip packaged in a 474-pin plastic ball grid array (PBGA). Figure 4–2 shows the AlphaPC 164LX implementation of the 21174 core logic chip.
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21174 Core Logic Chip 4.2.1 21174 Chip Overview The 21174 application-specific integrated circuit (ASIC) accepts addresses and commands from the 21164 microprocessor and drives the main memory array with the address, control, and clock signals. It also provides an interface to the 64-bit PCI I/O bus. The 21174 chip provides the following functions: • Serves as the interface between the 21164 microprocessor, main memory (addressing and control), and the PCI bus.
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21174 Core Logic Chip The AlphaPC 164LX supports a maximum of 512MB of main memory. The memory is organized as two banks. Table 1–1 lists total memory options along with the corresponding DIMM sizes required. All CPU cacheable memory accesses and PCI DMA accesses are controlled and routed to main memory by the 21174 core logic chip. The AlphaPC 164LX implements the alternate memory mode for SDRAM RAS and CAS control signals.
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21174 Core Logic Chip the configuration and operating frequencies, the PCI bus supports up to 264-MB/s (33 MHz, 64-bit) peak throughput. The PCI provides parity on address and data cycles. Three physical address spaces are supported: • 32-bit memory space • 32-bit I/O space • 256-byte-per-agent configuration space The bridge from the 21164 system bus to the 64-bit PCI bus is provided by the 21174 chip. It generates the required 32-bit PCI address for 21164 I/O accesses directed to the PCI.
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ISA Bus Devices 4.2.5 PCI Expansion Slots Four dedicated PCI expansion slots are provided on the AlphaPC 164LX. This allows the system user to add additional 32-bit or 64-bit PCI options. While both the 32-bit and the 64-bit slots use the standard 5-V PCI connector and pinout, +3.3 V is supplied for those boards that require it. The SIO chip provides the interface to the ISA expansion I/O bus. 4.
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ISA Bus Devices • Keyboard/mouse–An 8042-compatible interface is brought out to separate 6-pin DIN connectors (J5). • Time-of-year clock–A DS1287-compatible clock is backed up by a replaceable battery. An onboard clock generator chip supplies a 14.3-MHz reference clock for the diskette data separator and serial ports. Figure 4–4 AlphaPC 164LX ISA Bus Devices PCI Bus PCI-to-ISA Bridge 82378ZB la<23:17> ISA0 ISA1 pc164lx.23 pc164lx.23 sd<15:0> sd<7:0> Transceivers ubus_data<7:0> pc164lx.
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ISA Bus Devices 4.3.2 Utility Bus Memory Device The AlphaPC 164LX Ubus drives a flash ROM memory device. The flash ROM chip provides 1MB of flash memory for operating system support. Flash data is accessed through 20 address inputs. The low-order 19 address bits are driven by ISA bus sa<18:0>. The high-order 20th bit (flash_adr19) is driven by the Ubus decode PLA. Address bit flash_adr19 can be changed by writing to ISA I/O port x800.
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Interrupts Table 4–1 ISA I/O Address Map (Continued) Range (hex) Usage 800 FLASH_ADR19 register 801 AlphaPC 164LX configuration register 804-806 PCI interrupt registers 4.3.5 Flash ROM Address Map The address range for the flash ROM is FFF8.0000–FFFF.FFFF. Flash space of 1MB is obtained by double mapping this 512KB space. FLASH_ADR19 register at I/O location 80016 provides this function. Writing a 0 to this location enables the lower 512KB of flash.
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9 March 1999 – Subject To Change * x can vary from a to d; n can vary from 0 to 3. drq<7:5, 3:0> irq<15:3,1> irq<15:4> pc164lx.23 ISA Slots pc164lx.18 ide_int_l * pci_int xn _l IDE Controller pc164lx.20-21 PCI Slots <3:0> pc164lx.25 Combination Controller <15:9,7:3,1> sio_int pci_isa_irq Ubus<7:0> pc164lx.17 System Interrupt PLD PCI Bus pc164lx.22 PCI-to-ISA Bridge pc164lx.7 21174 sio_nmi cia_error pc164lx.3 pc164lx.3 pc164lx.
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Interrupts Table 4–2 AlphaPC 164LX System Interrupts 21164 Interrupt IPL1 Suggested Usage AlphaPC 164LX Usage cpu_irq<0> 20 Corrected system error Corrected ECC error and sparse space reserved encodings detected by the 21174 cpu_irq<1> 21 — PCI and ISA interrupts cpu_irq<2> 22 Interprocessor and timer TOY clock interrupt interrupts cpu_irq<3> 23 — Reserved pwr_fail_irq 30 Powerfail interrupt Reserved sys_mch_chk_irq 31 System machine check interrupt SIO NMI and 21174 errors mch_hl
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Interrupts Table 4–3 ISA Interrupts (Continued) Interrupt Number Interrupt Source IRQ9 Available IRQ10 Available IRQ11 Available IRQ12 Mouse IRQ13 Available IRQ14 IDE IRQ15 IDE 1 The # symbol indicates an active low signal. 4.4.1 Interrupt PLD Function The MACH210A PLD is an 8-bit I/O slave on the ISA bus at hex addresses 804, 805, and 806. This is accomplished by a decode of the three ISA address bits sa<2:0> and the three ecas_addr<2:0> bits.
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System Clocks Figure 4–6 Interrupt/Interrupt Mask Registers ISA Address 804 7 6 INTB0 Reserved ISA Address 805 7 6 INTD0 INTC3 ISA Address 806 7 6 Reserved 5 4 3 2 1 0 IDE SIO INTA3 INTA2 INTA1 INTA0 5 4 3 2 1 0 INTC2 INTC1 INTC0 INTB3 INTB2 INTB1 5 4 3 2 1 0 INTD3 INTD2 INTD1 Reserved Reserved Reserved Reserved MK2306-37 4.5 System Clocks Figure 4–7 shows the AlphaPC 164LX clock generation and distribution scheme.
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System Clocks • Miscellaneous clocks — The miscellaneous clocks include those needed for ISA and the combination controller. These clocks are provided by a crystal and a frequency generator with fixed scaling. Figure 4–7 AlphaPC 164LX System Clocks clk_in_h Microprocessor Clock Synthesizer (MC12439) 21164 Microprocessor clk_in_l pc164lx.3 irq_h<3:0> J27 Jumpers CY2308 PLL pc164lx.
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Reset and Initialization At system reset, the 21164 microprocessor’s irq_h<3:0> pins are driven by the clock divisor values set by four jumpers on J27. During normal operation, these signals are used for interrupt requests. The pins are either switched to ground or pulled up in a specific combination to set the 21164 microprocessor’s internal divider. The 21164 microprocessor produces the divided clock output signal sys_clk_out1 that drives the CY2308 PLL clock-driver chip.
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Serial ROM Figure 4–8 System Reset and Initialization J3 pc164lx.31 Power Sense shdn_l +3 V To +2.5-V Regulator pc164lx.32 J18 pc164lx.28 fan_ok_l 2 SIO 21174 pc164lx.22 pc164lx.7 Fan Sensor J21 pc164lx.30 pc164lx.28 1 rst_l Buffering Debounce sys_reset(n)_l irq_reset_l sys_reset_l 2 b_dcok Reset Switch dc_ok_h pc164lx.30 System Reset IRQ Mux 21164 pc164lx.29 J3 pc164lx.2 pc164lx.31 8 p_dcok Power Supply FM-05951.AI4 4.
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DC Power Distribution microprocessor and SROM (such as the clock). Connector J29 supports an RS-232 or RS-422 terminal connection to this port by using 1488 and 1489 line driver and receiver components. Additional external logic is not required. Figure 4–9 Serial ROM srom_dat_h 21164 srom_oe_l SROM real_srom_d MUX srom_clk_h pc164lx.2 2 5 pc164lx.3 pc164lx.3 srom_clk_l test_srom_d test_srom_d_l J29 pc164lx.26 pc164lx.3 FM-05952.AI4 4.
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9 March 1999 – Subject To Change pc164lx.31 1,2,11 3,5,7,13 15,16,17 18 4,6,19,20 12 10 +3.3 V Gnd -5 V +3.3-V Pull-Ups pc164lx.23 ISA Conn. +12 V -12 V +5 V (Vdd) Power Connector J3 pc164lx.21 PCI64 Conn. pc164lx.20 PCI32 Conn. Spkr Pull-Downs +5-V Pull-Ups pc164lx.32 +2.5-V Regulator +2V Integrated Circuits/Clocks Flash pc164lx.28 Fan FM-05953.AI4 pc164lx.2 21164 P/J18 Fans J2, J19 DC Power Distribution Vdd (+5.
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5 Upgrading the AlphaPC 164LX For higher system speed or greater throughput, you can upgrade SDRAM memory by replacing DIMMs with those of greater size. When configuring or upgrading SDRAM, observe the following rules: • Each DIMM must be a 168-pin unbuffered version and have a frequency of 100 MHz. • All DIMMs must be of equal size if they are in the same bank. 5.1 Configuring SDRAM Memory Although not an exhaustive list, Table 5–1 lists the tested SDRAM memory configurations available.
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Upgrading SDRAM Memory Table 5–1 AlphaPC 164LX SDRAM Memory Configurations Bank 0 Total Memory 32MB 64MB 96MB 128MB 160MB 192MB 256MB 512MB J8 2Mb X 72 2Mb X 72 4Mb X 72 4Mb X 72 4Mb X 72 8Mb X 72 8Mb X 72 8Mb X 72 8Mb X 72 16Mb X 72 16Mb X 72 Bank 1 J9 2Mb X 72 2Mb X 72 4Mb X 72 4Mb X 72 4Mb X 72 8Mb X 72 8Mb X 72 8Mb X 72 8Mb X 72 16Mb X 72 16Mb X 72 J10 — 2Mb X 72 — 2Mb X 72 4Mb X 72 — 2Mb X 72 4Mb X 72 8Mb X 72 — 16Mb X 72 J11 — 2Mb X 72 — 2Mb X 72 4Mb X 72 — 2Mb X 72 4Mb X 72 8Mb X 72 — 16Mb
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Increasing Microprocessor Speed 5.3 Increasing Microprocessor Speed This section describes how to complete the following actions to increase microprocessor speed: • Replace the Alpha 21164 microprocessor with an Alpha chip that has a higher speed rating. • Reconfigure the clock divisor jumpers. 5.3.
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Increasing Microprocessor Speed 5.3.3 Removing the 21164 Microprocessor Remove the microprocessor currently in place at location U40 by performing the following steps: 1. Unplug the fan power/sensor cable from connector J18 (see Figure 2–1). 2. Remove the four 6-32 X 0.875-inch screws that secure the fan and fan guard to the heat sink. 3. Remove the fan and fan guard. 4. If the sink/chip/fan clip is used, remove it by unhooking its ends from around the ZIF socket retainers. 5.
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Increasing Microprocessor Speed 6. Install the heat sink and heat-sink fan as directed in the following steps. A heatsink/fan kit is available from the vendor listed in Appendix B. Refer to Figure 5–1 for heat-sink and fan assembly details. Figure 5–1 Fan/Heat-Sink Assembly Screw, 6-32 x 0.875 in Qty 4 Guard, Fan Fan Clip, Heat Sink/Chip/Fan Nut, Hex, 1/4-20, 2011-T3 Aluminum, 0.
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Increasing Microprocessor Speed 2. Wearing clean gloves, pick up the GRAFOIL pad. Do not perform this with bare hands because skin oils can be transferred to the pad. 3. Place the GRAFOIL pad on the gold-plated slug surface and align it with the threaded studs. b. Attach the microprocessor heat sink. The heat-sink material is clear anodized, hot-water-sealed, 6061-T6 aluminum. The nut material is 2011-T3 aluminum (this grade is critical). Perform the following steps to attach the heat sink: 1.
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A System Address Space This appendix describes the mapping of 21164 40-bit physical addresses to memory and I/O space addresses. It also describes the translation of a 21164-initiated address (addr_h<39:4>) into a PCI address (ad<63:0>) and the translation of a PCI-initiated address into a physical memory address. PCI addressing topics include dense and sparse address space and scatter-gather address translation for DMA operations. A.
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Address Map Table A–1 Physical Address Map (Byte/Word Mode Disabled) (Continued) 21164 Address1 Size (GB) Selection 87.2000.0000 – 87.3FFF.FFFF 0.50 PCI special/interrupt acknowledge 87.4000.0000 – 87.4FFF.FFFF 0.25 21174 main CSRs 87.5000.0000 – 87.5FFF.FFFF 0.25 21174 memory control CSRs 87.6000.0000 – 87.6FFF.FFFF 0.25 21174 PCI address translation 87.7000.0000 – 87.7FFF.FFFF 0.25 Reserved 87.8000.0000 – 87.8FFF.FFFF 0.25 21174 miscellaneous CSRs 87.9000.0000 – 87.9FFF.FFFF 0.
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Address Map Table A–2 Physical Address Map (Byte/Word Mode Enabled) (Continued) 21164 Address Size (GB) Selection 87.6000.0000 – 87.6FFF.FFFF 0.25 21174 PCI address translation 87.7000.0000 – 87.7FFF.FFFF 0.25 Reserved 87.8000.0000 – 87.8FFF.FFFF 0.25 21174 miscellaneous CSRs 87.9000.0000 – 87.9FFF.FFFF 0.25 21174 power management CSRs 87.A000.0000 – 87.AFFF.FFFF 0.25 21174 interrupt control CSRs 87.B000.0000 – 87.BFFF.FFFF 0.25 Reserved 88.0000.0000 – 88.FFFF.FFFF 4.
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Address Map The 21164 address space is divided into two regions using physical address <39>: • 0 – 21164 access is to the cached memory space. • 1 – 21164 access is to noncached space. This noncached space is used to access memory-mapped I/O devices. Mailboxes are not supported. The noncached space contains the CSRs, noncached memory space (for diagnostics), and the PCI address space.
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Address Map Figure A–1 Address Space Overview 21164 Environment Main System Memory PCI Memory Space PCI Window PCI Device 21164 PCI Device PCI I/O Space CSRs PCI Configuration Space LJ-05395.AI4 DMA access to the system memory is achieved using windows in one of the following three ways: • Directly, using the “Monster Window” with dual-address cycles (DAC), where ad<33:0> equals addr_h<33:0>. • Directly-mapped, by concatenating an offset to a portion of the PCI address.
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PCI Address Space Figure A–2 Memory Remapping 21164 CPU Cached Memory Space (8GB) PCI Memory Space 8KB Page PCI Window Direct Map PCI Window Scatter-Gather Map LJ-05396.AI4 A.2 PCI Address Space The system generates 32-bit PCI addresses but accepts both 64-bit address (DAC1) cycles and 32-bit PCI address (SAC2) cycles. Accessing main memory is as follows: • Window 4, the “Monster Window,” provides full access to main memory. It is accessed by DAC only with ad<40> equal to 1.
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21164 Address Space A.3 21164 Address Space Figure A–3 shows an overview of the 21164 address space. Figure A–4 shows how the 21164 address map translates to the PCI address space and how PCI devices access the 21164 memory space using DMA transactions. The PCI memory space is double mapped via dense and sparse space. The 21164 I/O address map has the following characteristics: • Provides 4GB of dense3 address space to completely map the 32-bit PCI memory space.
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21164 Address Space Figure A–3 21164 Address Space Configuration 21164 Memory Space Cached Memory Scatter-Gather or Direct Translation PCI Windows Reserved PCI Memory Space PCI Memory Dense Space PCI I/O Space PCI Memory Sparse Space PCI I/O Space 21164 Programmed I/O DMA Read/Write LJ-05397.
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21164 Address Space Figure A–4 21164 and DMA Read and Write Transactions 39 38 37 36 35 34 33 32 31 30 Size 00 Physical Address 0 000XX 00.0000.0000 8GB Cached Memory 01.FFFF.FFFF 02.0000.0000 Reserved 0=Cached Memory Space 1=Noncached I/O Space 00XXX 7F.FFFF.FFFF 80.0000.0000 0100X 83.FFFF.FFFF 84.0000.0000 01010 84.FFFF.FFFF 85.0000.0000 01011 85.8000.0000 0110X 86.0000.0000 PCI Memory Sparse Space 704MB Maximum PCI I/O Sparse Space — 64MB PCI Memory Dense Space — 4GB 0111X 86.FFFF.
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21164 Address Space A.3.1 System Address Map Figure A–5 shows the following system address regions: • Main memory address space contains 8GB. All transactions contain 64 bytes, are cache-block aligned, and are placed in cache by the 21164. Both Istream and Dstream transactions access this address space. • PCI sparse-space memory region 1 contains 512MB. Noncached 21164 read/write transactions are allowed, including byte, word, tribyte, longword (LW), and quadword (QW) types.
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21164 Address Space Figure A–5 System Address Map Main Memory — 8GB 39 38 35 34 33 4 3 0 Memory Address 0 0 0 0 0 0 PCI Sparse Memory Space — 512MB Region 1 39 38 35 34 33 7 6 PCI Memory Address <28:2> 1 0 X 0 0 0 3 2 0 Size 0 0 0 PCI Sparse Memory Space — 128MB Region 2 39 38 7 6 35 34 33 32 31 PCI Memory Address <26:2> 1 0 X 0 0 1 0 0 3 2 1 0 Size 0 0 0 PCI Sparse Memory Space — 64MB Region 3 39 38 35 34 33 32 31 30 7 6 PCI Memory Address <25:2> 1 0 X 0 0 1 0 1 0 3 2 1 0 Size
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21164 Byte/Word PCI Space Figure A–6 21174 CSR Space PCI Configuration Space 39 38 35 34 33 32 31 1 0 X 0 0 1 1 1 CPU Address 31 30 29 28 28 27 7 6 CSR Space Size (GB) Address Size 0 0 0 Contents 0 0 0 0.5 PCI Configuration Space 0 0 1 0.5 PCI IACK/Special Cycle 0 1 0 0 0.25 21174 Main CSRs 0 1 0 1 0.25 Main Memory Control CSRs 0 1 1 0 0.25 21174 Address Translation 0 1 1 1 0.25 Reserved 2.00 Miscellaneous 1 3 2 1 0 FM-06062.AI4 A.
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21164 Byte/Word PCI Space Figure A–7 Byte/Word PCI Space PCI Memory Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 0 0 2 1 0 PCI Memory Address <31:2> 0 0 PCI I/O Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 0 1 0 PCI I/O Address PCI Type 0 Configuration Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 1 0 2 1 0 PCI Configuration Address <31:2> 0 0 PCI Type 1 Configuration Space — 4GB 39 38 37 36 35 34 33 32 31 1 Size X 1 0 1 1 2 1 0 PCI Configuration Address <31:2> 0 1 LJ
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21164 Byte/Word PCI Space Table A–3 shows noncached 21164 addresses when byte/word support is enabled. Table A–3 21164 Byte/Word Addressing Instruction addr_h <38:37> int4_valid <3> <2> <1> <0> LDQ 00 INT8 — — — LDL 01 addr_h<3:2> — Undefined — LDWU 10 addr_h<3:1> — — Undefined LDBU 11 addr_h<3:0> — — — STQ 00 INT4 Mask — — — STL 01 INT4 Mask — — — STW 10 addr_h<3:1> — — Undefined STB 11 addr_h<3:0> — — — A.4.
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Cacheable Memory Space A.5 Cacheable Memory Space Cacheable memory space is located in the range 00.0000.0000 to 01.FFFF.FFFF. The 21174 recognizes the first 8GB to be in cacheable memory space. The block size is fixed at 64 bytes. Read and flush commands to the 21164 caches occur for DMA traffic. A.6 PCI Dense Memory Space PCI dense memory address space is located in the range 86.0000.0000 to 86.FFFF.FFFF.
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PCI Dense Memory Space • The concept of dense space (and sparse space) is applicable only to a 21164-generated address. There is no such thing as dense space (or sparse space) for a PCI generated address. • Byte or word transactions are not possible in dense space. The minimum access granularity is a longword on write transactions and a quadword on read transactions. The maximum transfer length is 32 bytes (performed as a burst of eight longwords on the PCI).
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PCI Sparse Memory Space Figure A–8 shows dense-space address generation. Figure A–8 Dense-Space Address Generation 21164 Address 39 38 1 35 34 33 32 31 05 04 02 01 00 1 1 0 00 <31:5> int4_valid 21164 PCI Dense Memory Address 31 05 04 02 01 00 00 LJ04264A.AI4 The following list describes address generation in dense space: • addr_h<31:5> value is sent directly out on ad<31:5>. • addr_h<4:2> is not sent out by the 21164 and instead is inferred from the int4_valid<3:0>.
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PCI Sparse Memory Space A.7.1 Hardware Extension Register (HAE_MEM) In sparse space, addr_h<7:3> are used to encode byte enable bits, size bits and the low-order PCI address, ad<2:0>. This means that there are now five fewer address bits available to generate the PCI physical address. The system provides three sparse-space PCI memory regions and allows all three sparse-space regions to be relocated by way of bits in the HAE_MEM register. This provides software with great flexibility. A.7.
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PCI Sparse Memory Space • Hardware does not perform read-ahead (prefetch) transactions in sparse space because read-ahead transactions may have detrimental side effects. • Programmers are required to insert memory barrier (MB) instructions between sparse-space transactions to prevent collapsing in the 21164 write buffer. However, this is not always necessary. For example, consecutive sparse-space addresses will be separated by 32 bytes (and will not be collapsed by the 21164).
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PCI Sparse Memory Space Table A–6 defines the low-order PCI sparse memory address bits. Signals addr_h<7:3> are used to generate the length of the PCI transaction in bytes, the byte enable bits, and ad<2:0>. The 21164 signals addr_h<30:8> correspond to the quadword PCI address and are sent out on ad<25:3>. Table A–6 PCI Memory Sparse-Space Read/Write Encodings Size addr_h<4:3> Byte Word4 00 01 Byte Offset addr_h <6:5> ad<2:0> Data-In Register PCI Byte Byte Lanes Enable1 63.....32 31.......
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PCI Sparse Memory Space The high-order ad<31:26> are obtained from either the hardware extension register (HAE_MEM) or the 21164 address depending on sparse-space regions, as shown in Table A–7. See the 21174 Core Logic Chip Technical Reference Manual for more information about the 21174 HAE_MEM CSR. Table A–7 PCI Address Mapping 21164 Address Region ad <31> <30> <29> <28> <27> <26> CPU<32> CPU<31> 80.0000.0000 to 1 83.FFFF.FFFF HAE_MEM HAE_MEM HAE_MEM CPU<33> <31> <30> <29> 84.0000.
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PCI Sparse Memory Space Figure A–10 PCI Memory Sparse-Space Address Generation – Region 2 21164 Address 35 34 33 32 31 39 38 SBZ 1 1 0 0 08 07 06 05 04 03 02 00 PCI QW Address int4_valid 21164 HAE_MEM CSR 31 16 15 11 10 00 43 31 Length in Bytes Byte Offset 03 02 01 00 27 26 0 0 PCI Address LJ-04266.AI4 Figure A–11 shows the mapping for region 3.
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PCI Sparse I/O Space A.8 PCI Sparse I/O Space The PCI sparse I/O space is divided into two regions — region A and region B. Region A addresses the lower 32MB of PCI I/O space and is never relocated. This region will be used to address the (E)ISA devices. Region B is used to address a further 32MB of PCI I/O space and is relocatable using the HAE_IO register. A.8.
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PCI Sparse I/O Space Table A–8 contains the PCI sparse I/O space read/write encodings. Table A–8 PCI Sparse I/O Space Read/Write Encodings Size addr_h<4:3> Byte Word 00 3 01 Byte Offset addr_h <6:5> 21164 Instruction Allowed Data-In Register Byte Lanes 63.....32 31.......
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PCI Sparse I/O Space Figure A–12 PCI Sparse I/O Space Address Translation (Region A, Lower 32MB) 21164 Address 35 34 33 32 31 30 29 39 38 1 SBZ 08 07 06 05 04 03 02 00 1 0 1 1 0 <29:8> int4_valid 21164 43 31 25 24 Length in Bytes Byte Offset 03 02 01 00 0 0 0 0 0 0 0 0 0 PCI Address LJ-04268.
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PCI Configuration Space A.9 PCI Configuration Space The PCI configuration space is located in the range 87.0000.0000 to 87.1FFF.FFFF. Software is advised to clear PYXIS_CTRL when probing for PCI devices by way of configuration space read transactions. This will prevent the 21174 from generating an ECC error if no device responds to the configuration cycle (and random data is picked up on the PCI bus).
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PCI Configuration Space Figure A–14 PCI Configuration Space Definition (Sparse) CPU Address 39 38 1 35 34 MBZ 32 31 29 28 21 20 16 15 13 12 07 06 05 04 03 02 00 1 1 1 0 0 0 Length Byte Offset CFG<1:0> Type 0 PCI Configuration Address Type 1 PCI Configuration Address 31 11 10 IDSEL 31 27 26 Function 24 23 0 0 0 0 0 0 0 0 08 07 16 15 Bus 11 10 Device 02 01 00 Register 08 07 Function 0 0 02 01 00 Register 0 1 LJ04270A.
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PCI Configuration Space Peripherals are selected during a PCI configuration cycle if the following three conditions are met: 1. Their IDSEL pin is asserted. 2. The PCI bus command indicates a configuration read or write. 3. Address bits <1:0> are 00. Address bits <7:2> select a Dword (longword) register in the peripheral’s 256-byte configuration address space. Transactions can use byte masks.
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PCI Configuration Space Note: If a quadword access is specified for the configuration cycle, then the least significant bit of the register number field (such as ad<2>) must be zero. Quadword transactions must access quadword aligned registers. If the PCI cycle is a configuration read or write cycle but the ad<1:0> are 01 (that is, a type 1 transfer), then a device on a hierarchical bus is being selected via a PCI-toPCI bridge.
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PCI Configuration Space archically behind it. If the bus number of the configuration cycle matches the bus number of the bridge chip’s secondary PCI interface, it will accept the configuration cycle, decode it, and generate a PCI configuration cycle with ad<1:0> = 00 on its secondary PCI interface. If the bus number is within the range of bus numbers that may exist hierarchically behind its secondary PCI interface, the bridge chip passes the PCI configuration cycle on unmodified (ad<1:0> = 01).
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PCI Special/Interrupt Cycles A.10 PCI Special/Interrupt Cycles PCI special/interrupt cycles are located in the range 87.2000.0000 to 87.3FFF.FFFF. The Special cycle command provides a simple message broadcasting mechanism on the PCI. The Intel processor uses this cycle to broadcast processor status; but in general it may be used for logical sideband signaling between PCI agents. The special cycle contains no explicit destination address, but is broadcast to all agents.
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PCI to Physical Memory Address The address space here is a hardware-specific variant of sparse-space encoding. For the CSRs, addr_h<27:6> specifies a longword address where addr_h<5:0> must be zero. All the 21174 registers are accessed with a LW granularity. For more specific details on the 21174 CSRs, see the DIGITAL 21174 Core Logic Chip Technical Reference Manual. For the flash ROM, addr_h<30:6> defines a byte address. The fetched byte is always returned in the first byte lane (bits <7:0>). A.
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PCI to Physical Memory Address Table A–12 shows the PCI target window mask fields.
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PCI to Physical Memory Address The window base address must be on a naturally aligned boundary address depending on the size of the window6. This rule is not particularly difficult to obey, because the address space of any PCI device can be located anywhere in the PCI’s 4GB memory space, and this scheme is compatible with the PCI specification: A PCI device specifies the amount of memory space it requires via the Base registers in its configuration space.
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PCI to Physical Memory Address Figure A–17 PCI DMA Addressing Example 21164 System PCI Device's DMA Memory Space 8KB Page Scatter-Gather Map 21164 Memory Space (8GB) PCI Memory Space (4GB) PCI Device 0 PCI Device 1 PCI Device 2 LJ-05402.AI4 Figure A–18 shows the PCI window logic. The comparison logic associated with ad<63:32> is only used for DAC9 mode; and only if enabled by a bit in the window base register for window 3. This logic is only applicable to window 3.
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PCI to Physical Memory Address Figure A–18 PCI Target Window Compare PCI Address 63 40 Zero Detect 32 39 Compare & Hit Logic 31 n n-1 02 20 19 Hit (Window 3 Only) Target Window Hit Logic Hit Window 3 Hit Window 2 Hit Window 1 Hit Window 0 W_DAC Window Enable (WENB) 31 n n-1 Wn_BASE DAC 31 Wn_MASK 20 XXXXX n n-1 00000000 Window 3 SG Bit Window 2 SG Bit Window 1 SG Bit Window 0 SG Bit 20 11111 LJ04273A.
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Direct-Mapped Addressing A.13 Direct-Mapped Addressing The target address is translated by direct mapping or scatter-gather mapping as determined by the Wx_BASE_SG (scatter-gather) bit of the window’s PCI base register. If the Wx_BASE_SG bit is clear, the DMA address is direct mapped, and the translated address is generated by concatenating bits from the matching window’s translated base register (T_BASE) with bits from the incoming PCI address.
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Scatter-Gather Addressing Table A–13 Direct-Mapped PCI Target Address Translation (Continued) W_MASK<31:20> Size of Window Translated Address <32:2> 0111 1111 1111 2GB Translated Base<33:31> : ad<30:2> 1111 1111 1111 4GB Translated Base<33:32> : ad<31:2> Otherwise Not supported — A.14 Scatter-Gather Addressing If the Wx_BASE_SG bit of the PCI base register is set, then the translated address is generated by a lookup table. This table is called a scatter-gather map.
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Scatter-Gather Addressing Each scatter-gather map page table entry (PTE) is a quadword and has a valid bit in bit position 0, as shown in Figure A–19. Address bit 13 is at bit position 1 of the map entry. Because the 21174 implements valid memory addresses up to 16GB, then bits <63:22> of the scatter-gather map entry must be programmed to 0. Bits <21:1> of the scatter-gather map entry are used to generate the physical page address.
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Scatter-Gather TLB Table A–14 Scatter-Gather Mapped PCI Target Address Translation (Continued) W_MASK<31:20> Size of SG Map Table Translated Address <32:2> 0000 0001 1111 32KB Translated Base<33:15> : ad<24:13> 0000 0011 1111 64KB Translated Base<33:16> : ad<25:13> 0000 0111 1111 128KB Translated Base<33:17> : ad<26:13> 0000 1111 1111 256KB Translated Base<33:18> : ad<27:13> 0001 1111 1111 512KB Translated Base<33:19> : ad<28:13> 0011 1111 1111 1MB Translated Base<33:20> : ad<29:13> 01
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Scatter-Gather TLB Figure A–20 Scatter-Gather Associative TLB PCI DAC Address Cycle <31:15> 8KB CPU Page Address Hit TAG V V V V V V V V V V V V V V V V DATA V V V V V V V V V V V V V V V V PCI Address<14:13> Memory Page Address<32:13> Physical Memory Dword Address PCI Address<12:2> Index LJ04276A.AI4 Each time an incoming PCI address hits in a PCI target window that has scattergather translation enabled, ad<31:15> are compared with the 32KB PCI page address in the TLB tag.
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Scatter-Gather TLB mapping. Both paths are indicated — the right side shows the path for a TLB hit, while the left side shows the path for a TLB miss. The scatter-gather TLB is shown in a slightly simplified, but functionally equivalent form. A.15.1 Scatter-Gather TLB Hit Process The process for a scatter-gather TLB hit is as follows: 1. The window compare logic determines if the PCI address has hit in one of the four windows, and the PCI_BASE bit determines if the scatter-gather path should be taken.
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Scatter-Gather TLB Figure A–21 Scatter-Gather Map Translation 63 40 39 32 31 n n-1 20 19 02 13 12 0000000000000000000 Window Hit Offset Compare Logic 31 W_DAC n n-1 ad_h<31:13> sent to TLB for PCI window "hit." 20 XXXXX Wn_BASE DAC indicator also sent.
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Suggested Use of a PCI Window A.16 Suggested Use of a PCI Window Figure A–22 shows the PCI window assignment after power is turned on (configured by firmware), and Table A–15 lists the details. PCI window 0 was chosen for the 8MB to 16MB EISA region because this window incorporates the mem_cs_l logic. PCI window 3 was not used as it incorporates the DAC cycle logic. PCI window 1 was chosen arbitrarily for the 1GB, direct-mapped region, and PCI window 2 is not assigned.
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Suggested Use of a PCI Window Table A–15 lists the PCI window power-up configuration characteristics. Table A–15 PCI Window Power-Up Configuration PCI Window Assignment Size Comments 0 Scatter-gather 8MB Not used by firmware; mem_cs_l disabled 1 Direct-mapped 1GB Mapped to 0GB to 1GB of main memory 2 Disabled — — 3 Disabled — — A.16.
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Suggested Use of a PCI Window This mem_cs_l range in Figure A–23 is subdivided into several portions (such as the BIOS areas) that are individually enabled/disabled using CSRs as listed here: • The MCSTOM (top of memory) register has a 2MB granularity and can be programmed to select the regions from lMB up to 512MB. • The MCSTOH (top of hole) and MCSBOH (bottom of hole) registers define a memory hole region where mem_cs_l is not selected. The granularity of the hole is 64KB.
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Suggested Use of a PCI Window As shown in Figure A–24, PCI window 0 in the 21174 can be enabled to accept the mem_cs_l signal as the PCI memory decode signal. With this path enabled, the PCI window hit logic simply uses the mem_cs_l signal. For example, if mem_cs_l is asserted, then a PCI window 0 hit occurs and the devsel signal is asserted on the PCI. Figure A–24 mem_cs_l Logic mem_cs_l 1 PCI Address Wn_BASE Window 0 Hit Detect Logic 0 devsel Wn_MASK W0_BASE LJ-04280.
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B Support B.1 Customer Support The Alpha OEM website provides the following information for customer support. URL Description http://www.digital.
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Supporting Products B.2 Supporting Products This section contains information about sources for components and accessories that are not included with the AlphaPC 164LX. B.2.1 Memory Dual inline memory modules (DIMMs) are available from a variety of vendors. For a list of qualified vendors, visit the Alpha OEM World Wide Web Internet site at URL: http://www.digital.com/alphaoem Click on Technical Information. Then click on Alpha OEM Hardware Compatibility List. B.2.
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Alpha Products Antec, Inc. 2859 Bayview Drive Fremont, CA 94538 Phone: 510–770–1200, ext. 313 Contact: Han Liu PN PP–253X B.2.4 Enclosure An enclosure, suitable for housing the AlphaPC 164LX and its power supply, is available from: Delta Axxion Technology 1550 Northwestern Drive El Paso, TX 79912 Phone: 915–225–8888 PN DL17 B.3 Alpha Products To order the AlphaPC 164LX motherboard, contact your local distributor. The following tables list some of the Alpha products available.
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Alpha Documentation Design kits include full documentation and schematics. They do not include related hardware. Design Kits Order Number AlphaPC 164LX Motherboard Software Developer’s Kit (SDK) QR–21A04–12 B.4 Alpha Documentation The following table lists some of the available Alpha documentation. You can download Alpha documentation from the Alpha OEM World Wide Web Internet site: http://www.digital.com/alphaoem Click on Technical Information.
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Third–Party Documentation B.5 Third–Party Documentation You can order the following third-party documentation directly from the vendor. Title Vendor PCI Local Bus Specification, Revision 2.1 PCI Multimedia Design Guide, Revision 1.0 PCI System Design Guide PCI-to-PCI Bridge Architecture Specification, Revision 1.0 PCI BIOS Specification, Revision 2.1 PCI Special Interest Group U.S.
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Index Numerics C 21164 microprocessor. See Microprocessor. CAS, 4–5 21174 Core logic chip. See Core logic chip. Clocks, 1–4 14.3-MHz reference, 4–8 time-of-year, 4–8 Combination controller, 1–4, 4–7 21174-CA. See Core logic chip. 37C935. See Combination controller. 82378ZB. See SIO.
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Debug monitor system support, 1–5 Design support, 1–6 J Dimensions motherboard, 3–2 Direct mapping, 4–4 Jumper descriptions, 2–3 Jumper configurations, 2–4 DMA conversion, 4–4 Jumpers Bcache size, 2–5 boot option, 2–5 flash ROM update, 2–6 password bypass, 2–5 Documentation ordering, B–4 K E Keyboard controller, 4–8 Diskette controller, 4–7 Environmental requirements, 3–2 Extents and ranges, xii F Fan sensor, 3–1 FDC37C935. See Combination controller.
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N RO Numbering convention, xii RW definition, x definition, x O Operating systems software support, 1–5 Ordering products and documentation, B–3 P Packaging 21174 chip, 4–3 Parallel port, 4–7 PCI 21174 role, 4–6 bus, 4–5 bus hierarchy, A–30 bus speed, 4–5 configuration space, A–26 dense memory space, A–15 device implementation, 4–5 expansion slots, 4–7 interface, 1–4 memory remapping, A–6 sparse memory space, A–17 Pinouts connectors, 2–6 to 2–15 Power distribution, 4–18 monitor, 4–16 requirements, 3–1
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UNIX. See Tru64 UNIX. UNPREDICTABLE definition, xiii Upgrading memory, 5–2 microprocessor, 5–3 Utility bus. See Ubus.