Specifications

4–2 Functional Description 9 March 1999 – Subject To Change
AlphaPC 164LX Bcache Interface
4.1 AlphaPC 164LX Bcache Interface
The 21164 microprocessor controls the board-level L3 backup cache (Bcache) array
(see Figure 4–1). The data bus (data_h<127:0>), check bus (data_check_h<15:0>),
tag_dirty_h, and tag_ctl_par_h signals are shared with the system interface.
Figure 4–1 AlphaPC 164LX L3 Bcache Array
The Bcache is a 2MB, direct-mapped, synchronous SRAM (SSRAM) with a
128-bit data path. It is populated with a quantity of eight 9 ns, 128K
X 18
SSRAMs for data store, and one 9 ns, 64K
X 18 SSRAM for the tag store. In
most cases, wave-pipelined accesses can decrease the cache loop times by one
CPU cycle. The Bcache supports 64-byte transfers to and from memory.
21164
index_h<21:4>
idle_bc
Bcache
Data
Array
FM-05945.AI4
st_clk1_h
Microprocessor
pc164lx.5,6pc164lx.2
data_h<127:0>
tag_data_h<29:20>
tag_valid_h
tag_dirty_h
tag_ctl_par_h
data_check_h<15:0>
tag_data_par_h
tag_data_h<38:30>
SRAM
Tag
Array
(From 21174 Chip)
Buffer
pc164lx.4
data_ram_oe_h
data_ram_we_h
tag_ram_oe_h
tag_ram_we_h
st_clk1_<9:1>_h
index_h<21:6>