Technical Reference Guide For the Compaq iPAQ Internet Device
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Technical Reference Guide ii Compaq iPAQ Family of Internet Devices First Edition –- March 2000
Technical Reference Guide TABLE OF CONTENTS CHAPTER 1 INTRODUCTION............................................................................................................. 1.1 ABOUT THIS GUIDE ........................................................................................................... 1-1 1.1.1 USING THIS GUIDE ..................................................................................................... 1-1 1.1.2 ADDITIONAL INFORMATION SOURCES.....................................
Technical Reference Guide CHAPTER 4 SYSTEM SUPPORT......................................................................................................... 4.1 INTRODUCTION.................................................................................................................. 4-1 4.2 PCI BUS OVERVIEW ........................................................................................................... 4-2 4.2.1 PCI BUS TRANSACTIONS.............................................................
Technical Reference Guide 5.7 UNIVERSAL SERIAL BUS INTERFACE........................................................................... 5-22 5.7.1 USB DATA FORMATS ............................................................................................... 5-22 5.7.2 USB PROGRAMMING................................................................................................ 5-24 5.7.3 USB CONNECTOR .....................................................................................................
Technical Reference Guide CHAPTER 8 BIOS ROM ....................................................................................................................... 8.1 INTRODUCTION.................................................................................................................. 8-1 8.2 DESKTOP MANAGEMENT SUPPORT ............................................................................... 8-2 8.2.1 SYSTEM ID.................................................................................
Technical Reference Guide APPENDIX B ASCII CHARACTER SET ............................................................................................. B.1 INTRODUCTION..................................................................................................................B-1 APPENDIX C KEYBOARD ................................................................................................................... C.1 INTRODUCTION........................................................................
Technical Reference Guide LIST OF FIGURES FIGURE 2–1. FIGURE 2–2. FIGURE 2–3. FIGURE 2–4. FIGURE 2–5. FIGURE 2–6. FIGURE 2–7. COMPAQ IPAQ INTERNET DEVICE WITH MONITOR ............................................................. 2-1 COMPAQ IPAQ INTERNET DEVICE, FRONT VIEW................................................................ 2-4 COMPAQ IPAQ INTERNET DEVICE, REAR VIEWS ................................................................ 2-5 COMPAQ IPAQ INTERNET DEVICE CHASSIS LAYOUT, RIDE SIDE VIEW .
Technical Reference Guide FIGURE C–1. FIGURE C–2. FIGURE C–3. FIGURE C–4. FIGURE C–5. FIGURE C–6. FIGURE C–7. FIGURE C–8. FIGURE C–9. KEYSTROKE PROCESSING ELEMENTS, BLOCK DIAGRAM ....................................................C-2 PS/2 KEYBOARD-TO-SYSTEM TRANSMISSION, TIMING DIAGRAM ......................................C-3 U.S. ENGLISH (101-KEY) KEYBOARD KEY POSITIONS .......................................................C-5 NATIONAL (102-KEY) KEYBOARD KEY POSITIONS .................................
Technical Reference Guide LIST OF TABLES TABLE 1–1. ACRONYMS AND ABBREVIATIONS ....................................................................................... 1-3 TABLE 2-1. FEATURE DIFFERENCE MATRIX ........................................................................................... 2-2 TABLE 2-2. ARCHITECTURAL COMPARISON ............................................................................................. 2-8 TABLE 2-3. INTEL 810E CHIPSET COMPARISON ................................
Technical Reference Guide TABLE 5–19. TABLE 5–20. TABLE 5–21. TABLE 5–22. TABLE 5–23. TABLE 5–24. TABLE 5–25. AC’97 AUDIO CONTROLLER PCI CONFIGURATION REGISTERS ........................................ 5-30 AC’97 AUDIO CODEC CONTROL REGISTERS ................................................................... 5-30 AUDIO SUBSYSTEM SPECIFICATIONS ............................................................................... 5-31 AOL EVENTS ...................................................................
Technical Reference Guide xii Compaq iPAQ Family of Internet Devices First Edition –- March 2000
Technical Reference Guide Chapter 1 INTRODUCTION 1. Chapter 1 INTRODUCTION 1.1 ABOUT THIS GUIDE This guide provides technical information about the Compaq iPAQ Family of Internet Devices. This document includes information regarding system design, function, and features that can be used by programmers, engineers, technicians, and system administrators. This guide and any applicable addendum are available online at the following location: http://www.compaq.
Chapter 1 Introduction 1.3 NOTATIONAL CONVENTIONS 1.3.1 VALUES Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter “h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.” Numerical values that have no succeeding letter can be assumed to be decimal. 1.3.2 RANGES Ranges or limits for a parameter are shown using the following methods: Example A: Example B: Bits <7..4> = bits 7, 6, 5, and 4.
Technical Reference Guide 1.4 COMMON ACRONYMS AND ABBREVIATIONS Table 1-1 lists the acronyms and abbreviations used in this guide. Table 1–1. Acronyms and Abbreviations Table 1-1.
Chapter 1 Introduction Table 1-1.
Technical Reference Guide Table 1-1.
Chapter 1 Introduction 1-6 Compaq iPAQ Family of Internet Devices First Edition – March 2000
Technical Reference Guide Table 1-1.
Technical Reference Guide Chapter 2 SYSTEM OVERVIEW 2. Chapter 2 SYSTEM OVERVIEW 2.1 INTRODUCTION The Compaq iPAQ Family of Internet Devices provides affordable business solutions with the focus on internet access and mainstream performance. Based on an Intel Celeron or Pentium III processor with the Intel 810e chipset, these systems are designed to maximize the effectiveness of internet and intranet usage while simplifying system management. Figure 2–1.
Chapter 2 System Overview 2.2 FEATURES AND OPTIONS This section describes the standard features and available options. 2.2.
Technical Reference Guide 2.2.2 OPTIONS The following items are available as options for all models and may be included in the standard configuration of some models: ♦ System Memory: 32-MB DIMM (non-ECC) 64-MB DIMM (non-ECC) 128-MB DIMM (non-ECC) 256-MB DIMM (non-ECC) ♦ Hard drives: 4.3 or 8.4 GB UATA/66 hard drive ♦ MultiBay drives: 24x CD-ROM drive 4x DVD-ROM drive Super Disk LS-120 Power Drive 6.
Chapter 2 System Overview 2.3 MECHANICAL DESIGN The Compaq iPAQ Internet Device uses a minitower form factor featuring a smaller footprint and reduced height than previous minitowers, allowing easy floor or desktop positioning. Commonly used audio and USB connections are accessible from the front panel. There are slight differences between the legacy-light and legacy-free models, most notably in the rear panel layouts.
Technical Reference Guide 2.3.1.
Chapter 2 System Overview 2.3.2 CHASSIS LAYOUT The internal assemblies are accessible from the right side of the system unit. The right side (carbon-colored) cover is easily removable allowing quick access to the DIMM sockets through an access opening and to the hard drive. Access to the system board and processor requires removing the right chassis access panel. NOTE: For a detailed description on servicing the unit refer to the applicable Maintenance and Service Guide.
Technical Reference Guide 2.3.3 SYSTEM BOARD LAYOUTS The Compaq iPAQ Internet Device uses a FlexATX-type (9.0 x 7.5 inch) system board. Two variations are available; a legacy-light board and a legacy-free board.
Chapter 2 System Overview 2.4 SYSTEM ARCHITECTURE The Compaq iPAQ Internet Device features an Intel Celeron or Pentium III processor and the 810e chipset.
Technical Reference Guide Celeron or Pentium III Processor 66-/100-/133- MHz FSB 810e Chipset Monitor RGB AGP 2X Cntlr. 4-MB Display Cache PC100 Memory Bus 82810e-DC100 GMCH SDRAM Cntlr. SDRAM System Memory Hub Link Bus IDE Hard Drive MultiBay Device Pri. IDE I/F Sec.
Chapter 2 System Overview 2.4.1 PROCESSORS The Compaq iPAQ family includes models based on Celeron and Pentium III processors. These processors are backward-compatible with software written for the Pentium II, Pentium MMX, Pentium Pro, Pentium, and x86 microprocessors. Both processor architectures include a floatingpoint unit and first and secondary caches providing enhanced performance for multimedia applications. 2.4.1.1 Celeron Processor Select Compaq iPAQ systems use the Intel Celeron processor.
Technical Reference Guide 2.4.1.3 Processor Upgrading All models of the Compaq iPAQ use the PGA370 zero-insertion force (ZIF) socket for processor mounting as shown in Figure 2-7. Raising the Lock/Unlock handle of the socket in the vertical position allows the processor to be removed or inserted into the socket. Lowering the Lock/Unlock handle in the down (horizontal) position locks the processor in place. Factory configurations use processors fitted with passive heat sinks.
Chapter 2 System Overview 2.4.2 CHIPSET The Compaq iPAQ employs the Intel 810e chipset, which is designed to compliment the processor and provide the central point for the system’s data transactions. The chipset is composed of a graphics memory controller hub (GMCH), an I/O controller hub (ICH), and a firmware hub (FWH). Table 2-3 shows the functions provided by the components of the chipset. Table 2-3. Intel 810e Chipset Comparison Table 2-3.
Technical Reference Guide 2.4.3 SUPPORT COMPONENTS Input/output functions not provided by the chipset are handled by other support components. Some of these components also provide “housekeeping” and various other functions as well. Table 2-4 shows the functions provided by the support components. Table 2-4. Support Component Functions Table 2-4.
Chapter 2 System Overview 2.4.5 MASS STORAGE In a standard configuration the Compaq iPAQ supports two mass storage devices; one internal IDE hard drive mounted on the right side and a removeable-media IDE device (CD-ROM, DVD, or LS-120 Power Drive, etc.) mounted in the MultiBay on the left side. This system uses SMART drives for the internal IDE device. An adapter is available that allows a secondary IDE hard drive to be installed in the MultiBay.
Technical Reference Guide 2.4.9 AUDIO SUBSYSTEM The audio subsystem features an AC’97 specification-based design and uses the integrated AC97 audio controller of the chipset and an AC’97-compliant audio codec. Microphone and headphone jacks are accessible on the front panel and line input and output jacks are provided on the rear panel. A low-distortion 5-watt amplifier drives a long-excursion speaker for optimum sound. 2.
Chapter 2 System Overview Table 2-7. Physical Specifications Table 2-7. Physical Specifications Parameter Height Width Depth Weight Standard 11.80 in 5.66 in 9.44 in 10.7 lb Metric 29.97 cm 14.38 cm 23.98 cm 4.8 kg Table 2-8. MultiBay 24x CD-ROM Drive Specifications Table 2-8. MultiBay 24x CD-ROM Drive Specifications (SP# 161685-B21) Parameter Interface Type / Protocol Transfer Rate: Max. Sustained Burst Media Type Measurement IDE / ATAPI 3.6 MB/s 16.
Technical Reference Guide Table 2-9. MultiBay 24x CD-ROM Drive Specifications Table 2-9. MultiBay 4x DVD-ROM Drive Specifications (SP# 161685-B21) Parameter Interface Type / Protocol Transfer Rate: Max. Sustained (off disk) Data Bus Burst Media Types Measurement IDE / ATAPI 5.41 MB/s 16.
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Technical Reference Guide Chapter 3 PROCESSOR/ MEMORY SUBSYSTEM 3. Chapter 3 PROCESSOR/MEMORY SUBSYSTEM 3.1 INTRODUCTION This chapter describes the processor/cache memory subsystem of the Compaq iPAQ Internet Device featuring a Celeron or Pentium III processor and the 810e chipset (Figure 3-1). The 810e chipset supports up to two SDRAM DIMMs and integrates an i740 3D graphics controller (covered in Chapter 6).
Chapter 3 Processor/Memory Subsystem 3.2 PROCESSOR The Compaq iPAQ is configured as either a Celeron-based or Pentium III-based system. 3.2.1 CELERON PROCESSOR The Celeron processor (Figure 3-2) uses a dual-ALU CPU with branch prediction and MMX support, floating point unit (FPU) for math coprocessing, a 32-KB primary (L1) cache, and a 128-KB secondary (L2) cache. All internal functions, except for the front side bus interface (FSB I/F), operate at processor speed.
Technical Reference Guide 3.2.2 PENTIUM III PROCESSOR The Pentium III processor’s architecture (Figure 3-3) includes the same core functionality as described previously for the Celeron processor but includes a larger L2 cache and additional processing features. Pentium III 500E FPU 32-KB L1 Cache CPU FSB I/F Full processing speed 256-KB L2 or Cache Host bus speed Figure 3–3. Pentium III Processor Internal Architecture Table 3–2. Pentium III Processor Statistical Comparison Table 3-2.
Chapter 3 Processor/Memory Subsystem 3.2.3 PROCESSOR UPGRADING All units use the PGA370 ZIF mounting socket and ship with either a Celeron 500E or a Pentium III 500E installed. To replace the processor, use the following procedure: 1. 2. 3. 4. 5. 6. 7. Power down the system and disconnect the power cord. Remove the right outer (carbon) panel. Disconnect and remove the hard drive. Remove the right chassis access panel.
Technical Reference Guide 3.3 MEMORY SUBSYSTEM The 810e chipset supports PC100 SDRAM for system memory. The memory interface consists of a 64-bit data bus operating at 100 MHz providing a maximum throughput rate of 800 MB/s. The system board provides two 168-pin SDRAM DIMM sockets that accommodate single- or doublesided DIMMs. This system is designed for using non-ECC DIMMs only.
Chapter 3 Processor/Memory Subsystem The SPD address map is shown below. Table 3–3. SPD Address Map (SDRAM DIMM) Table 3-3. SPD Address Map (SDRAM DIMM) Byte 0 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NOTES: Description No. of Bytes Written Into EEPROM Total Bytes (#) In EEPROM Memory Type No. of Row Addresses On DIMM No. of Column Addresses On DIMM No.
Technical Reference Guide Figure 3-4 shows the system memory map. FFFF FFFFh FFE0 0000h FFDF FFFFh FEC1 0000h FEC0 FFFFh FEC0 0000h FEBF FFFFh Host, PCI, AGP Area 4 GB High BIOS Area (2 MB) PCI Memory (18 MB) APIC Config.
Chapter 3 Processor/Memory Subsystem 3.4 SUBSYSTEM CONFIGURATION The 82810e-DC100 GMCH component provides the configuration function for the processor/memory subsystem. Table 3-4 lists the configuration registers used for setting and checking such parameters as memory control and PCI bus operation. These registers reside in the PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2. Table 3–4. Host/PCI Bridge Configuration Registers (GMCH, Function 0) Table 3-4.
Technical Reference Guide Chapter 4 SYSTEM SUPPORT 4. Chapter 4 SYSTEM SUPPORT 4.1 INTRODUCTION This chapter covers subjects dealing with basic system architecture and support functions. Topics covered are: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ PCI bus overview (4.2) page 4-2 AGP bus overview (4.3) page 4-10 Interrupts (4.4) page 4-13 Interval timer (4.5) page 4-16 System clock distribution (4.6) page 4-16 Real-time clock and configuration memory (4.7) page 4-17 System management (4.8) page 4-27 System I/O map (4.
Chapter 4 System Support 4.2 PCI BUS OVERVIEW NOTE: This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.2. This system implements a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2) operating at 33 MHz. The PCI bus handles address/data transfers through the identification of devices and functions on the bus.
Technical Reference Guide 4.2.1 PCI BUS TRANSACTIONS The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle.
Chapter 4 System Support Figure 4-2 shows how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11> determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which acts as a “chip select” function for the PCI device to be configured. The function number (CF8h, bits <10..8>) is used to select a particular function within a PCI component.
Technical Reference Guide The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header. 31 24 23 16 15 8 7 0 Register Index FCh Device-Specific Area Min_Lat Min_GNT Interrupt Pin Interrupt Line 40h 3Ch Base Address Registers and Exp.
Chapter 4 System Support 4.2.2 PCI INTERRUPT MAPPING The PCI bus provides for four interrupt signals; INTA-, INTB-, INTC-, and INTD-. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots. In order to minimize latency, INTx- signal routing from the interrupt controller of the ICH to PCI slots/devices is distributed evenly as shown below: Intr. Cntlr. INTAINTBINTCINTD- AGP Cntlr. INTAINTB--- Audio Cntlr.
Technical Reference Guide 4.2.5 PCI CONFIGURATION PCI bus operations, especially those that involve ISA bus interaction, require the configuration of certain parameters such as PCI IRQ routing, DMA channel configuration, RTC control, port decode ranges, and firmware hub (FWH) access control. These parameters are handled by the LPC I/F bridge function (PCI function #0, device 31) of the ICH component and configured through the PCI configuration space registers listed in Table 4-3.
Chapter 4 System Support 4.3 AGP BUS OVERVIEW NOTE: This section provides a brief overview of AGP bus operation. For a detailed description of AGP bus operations refer to the AGP Interface Specification available at the following AGP forum web site: http://www.agpforum.org/index.htm The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet highperformance interface for graphics adapters, especially those designed for 3D operations.
Technical Reference Guide 4.3.1.1 Data Request Requesting data is accomplished in one of two ways; either multiplexed addressing (using the AD lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for addressing only and the AD lines for data only). Even though there are only eight SBA lines (as opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by allowing the AD lines to be exclusively used for data transfers.
Chapter 4 System Support AGP 2X Transfers During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66MHz CLK signal is used to qualify only the control signals. The data bytes are latched by an additional strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 45). The first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx and the second four bytes (DnB) are latched on the rising edge of AD_STBx.
Technical Reference Guide 4.3.2 AGP CONFIGURATION AGP bus operations require the configuration of certain parameters involving system memory access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device integrated within the north bridge (MCH, device 1) component. The AGP function is, from the PCI bus perspective, treated essentially as a PCI/PCI bridge and configured through PCI configuration registers (Table 4-4). Configuration is accomplished by BIOS during POST.
Chapter 4 System Support 4.4 INTERRUPTS The microprocessor uses two types of interrupts; maskable and nonmaskable. A maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor but may be inhibited by hardware or software means external to the microprocessor. 4.4.
Technical Reference Guide Table 4-5. Maskable Interrupt Priorities and Assignments Table 4-5.
Chapter 4 System Support 4.4.2 NON-MASKABLE INTERRUPTS Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may be maskable by software using logic external to the microprocessor. There are two non-maskable interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable interrupts, with the SMI- having top priority over all interrupts including the NMI-. 4.4.2.
Technical Reference Guide 4.4.2.2 SMI- Generation The SMI- (System Management Interrupt) is typically used for power management functions. When power management is enabled, inactivity timers are monitored. When a timer times out, SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with the APM BIOS to service the SMI- according to the cause of the timeout.
Chapter 4 System Support 4.5 INTERVAL TIMER The interval timer generates pulses at software (programmable) intervals. A 8254-compatible timer is integrated into the 82801 component. The timer function provides three counters, the functions of which are listed in Table 4-7. Table 4-7. Interval Timer Functions Table 4-7. Interval Timer Functions Counter 0 1 2 Function System Clock Refresh Speaker Tone Gate Always on Always on Port 61, bit<0> Clock In 1.193 MHz 1.193 MHz 1.
Technical Reference Guide 4.7 REAL-TIME CLOCK AND CONFIGURATION MEMORY The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the 82801 ICH component and is MC146818-compatible. As shown in the following figure, the 82801 ICH component provides 256 bytes of battery-backed RAM divided into two 128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard memory area.
Chapter 4 System Support Table 4-10 lists the mapping of the configuration memory. Table 4-10. Configuration Memory (CMOS) Map Table 4-10. Configuration Memory (CMOS) Map Location Function Location Function 00-0Dh Real-time clock 24h System board ID 0Eh Diagnostic status 25h System architecture data 0Fh System reset code 26h Auxiliary peripheral configuration 10h Diskette drive type 27h Speed control external drive 11h Reserved 28h Expanded/base mem.
Technical Reference Guide RTC Control Register A, Byte 0Ah Bit 7 6..4 3..0 Function Update in Progress. Read only. 0 = Time update will not occur before 2444 us 1 = Time update will occur within 2444 us Divider Chain Control. R/W. 00x = Oscillator disabled. 010 = Normal operation (time base frequency = 32.768 KHz). 11x = Divider chain reset. Periodic Interrupt Control. R/W. Specifies the periodic interrupt interval. 0000 = none 1000 = 3.90625 ms 0001 = 3.90625 ms 1001 = 7.8125 ms 0010 = 7.
Chapter 4 System Support Configuration Byte 0Eh, Diagnostic Status Default Value = 00h This byte contains diagnostic status data. Configuration Byte 0Fh, System Reset Code Default Value = 00h This byte contains the system reset code. Configuration Byte 10h, Diskette Drive Type Bit Function 7..4 Primary (Drive A) Diskette Drive Type 3..0 Secondary (Drive B) Diskette Drive Type Valid values for bits <7..4> and bits <3..0>: 0000 = Not installed 0001 = 360-KB drive 0010 = 1.
Technical Reference Guide Configuration Byte 13h, Security Functions Default Value = 00h Bit Function 7 Reserved 6 QuickBlank Enable After Standby: 0 = Disable 1 = Enable 5 Administrator Password: 0 = Not present 1 = Present 4 Reserved 3 Diskette Boot Enable: 0 = Enable 1 = Disable 2 QuickLock Enable: 0 = Disable 1 = Enable 1 Network Server Mode/Security Lock Override: 0 = Disable 1 = Enable 0 Password State (Set by BIOS at Power-up) 0 = Not set 1 = Set Configuration Byte 14h, Equipment Installed Default
Chapter 4 System Support Configuration Bytes 19h-1Ch, Hard Drive Types Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4> hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte 12h bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and 2 of the secondary controller.
Technical Reference Guide Configuration Byte 26h, Auxiliary Peripheral Configuration Default Value = 00h Bit Function 7,6 I/O Delay Select 00 = 420 ns (default) 01 = 300 ns 10 = 2600 ns 11 = 540 ns 5 Alternative A20 Switching 0 = Disable port 92 mode 1 = Enable port 92 mode 4 Bi-directional Print Port Mode 0 = Disabled 1 = Enabled 3 Graphics Type 0 = Color 1 = Monochrome 2 Hard Drive Primary/Secondary Address Select: 0 = Primary 1 = Secondary 1 Diskette I/O Port 0 = Primary 1 = Secondary 0 Diskette I/O Por
Chapter 4 System Support Configuration Byte 29h, Miscellaneous Configuration Data Default Value = 00h Bit Function 7..5 Reserved 4 Primary Hard Drive Enable (Non-PCI IDE Controllers) 0 = Disable 1 = Enable 3..0 Reserved Configuration Byte 2Ah, Hard Drive Timeout Default Value = 02h Bit Function 7..5 Reserved 4..
Technical Reference Guide Configuration Byte 2Dh, Additional Flags Default Value = 00h Bit Function 7..5 Reserved 4 Memory Test 0 = Test memory on power up only 1 = Test memory on warm boot 3 POST Error Handling (BIOS Defined) 0 = Display “Press F1 to Continue” on error 1 = Skip F1 message 2..0 Reserved Configuration Byte 2Eh, 2Fh, Checksum These bytes hold the checksum of bytes 10h to 2Dh.
Chapter 4 System Support Configuration Byte 35h, APM Status Flags Default Value = 11h Bit Function 7..
Technical Reference Guide 4.8 SYSTEM MANAGEMENT This section describes functions having to do with security, power management, temperature, and overall status. These functions are handled by hardware and firmware (BIOS) and generally configured through the Setup utility. 4.8.1 SECURITY FUNCTIONS These systems include various features that provide different levels of security.
Chapter 4 System Support 4.8.1.2 DriveLock Passwords This system supports the DriveLock security feature for a compatible hard drive installed in the Multibay. DriveLock, when enabled, prevents unauthorized access to hard drive data by requiring a master and/or user password to be entered for access to data on the hard drive. Although this function is configured through the Setup utility, the password information is stored in a reserved area on the hard drive (i.e.
Technical Reference Guide 4.9 SYSTEM I/O MAP Table 4-20 lists the fixed addresses of the input/output (I/O) ports. Table 4-11. System I/O Map Table 4-20. System I/O Map I/O Port Function 0000..000Fh DMA Controller 1 0020..0021h Interrupt Controller 1 0040..0043h Timer 1 0060h Keyboard Controller Data Byte 0061h NMI, Speaker Control 0064h Keyboard Controller Command/Status Byte 0070h NMI Enable, RTC/Lower CMOS Index 0071h RTC Data 0080..008Fh DMA Page Registers 0092h Port A, Fast A20/Reset 00A0..
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Technical Reference Guide Chapter 5 INPUT/OUTPUT INTERFACES 5. Chapter 5 INPUT/OUTPUT INTERFACES 5.1 INTRODUCTION This chapter describes the standard (i.e., system board) interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 5.2 Enhanced IDE interface (5.2) Diskette drive interface (5.3) Serial interfaces (5.4) Parallel interface (5.
Chapter 5 Input/Output Interfaces Hard drives types not found in the ROM’s parameter table are automatically configured as to (soft)type by DOS as follows: Primary controller: drive 0, type 65; drive 1, type 66 Secondary controller: drive 0, type 68; drive 1, type 15 Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive configuration. 5.2.1.1 IDE Configuration Registers The IDE controller is configured as a PCI device with bus mastering capability.
Technical Reference Guide 5.2.2 IDE CONNECTOR This system uses a standard 40-pin connector for the primary IDE device and connects (via a cable) to the hard drive installed in the right side drive bay. Note that some signals are re-defined for UATA/33 and UATA/66 modes, which require a special 80-conductor cable (supplied) designed to reduce cross-talk. Device power is supplied through a separate connector. Figure 5-1. 40-Pin Primary IDE Connector (on system board). Table 5–3.
Chapter 5 Input/Output Interfaces The system board includes a 50-pin connector for the secondary IDE drive that is installed in the MultiBay mounting position on the left side of the chassis. This interface includes power and audio signals. The 50-pin system/daughter board connector is illustrated below followed by the pinout. P2 P50 P1 P49 Figure 5-2. 50-Pin Secondary IDE Connector (on system and daughter boards). Table 5–4. 50-Pin Secondary IDE Connector Pinout Table 5-4.
Technical Reference Guide 5.4 SERIAL INTERFACE The legacy-light models include a serial interface to transmit and receive asynchronous serial data with external devices. The serial interface function is provided by the LPC47B277 I/O controller component that includes a NS16C550-compatible UART. NOTE: Legacy-free models do not have an externally accessible serial port, but do have an internal serial header to satisfy the serial port requirements of some operating systems.
Chapter 5 Input/Output Interfaces 5.4.2 SERIAL TEST INTERFACE Legacy-free systems do not provide an externally accessible serial port but do include a serial header connector on the system board to satisfy some the requirements of some operating systems. The test header and pinout is shown in the following figure: CD 1 2 DSR RX Data 3 TX Data 5 4 RTS 6 CTS DTR 7 8 RI Gnd 9 Figure 5-4. Serial Interface Header (on legacy-free system board) 5.4.
Technical Reference Guide Table 5–7. Serial Interface Control Registers Table 5-7. Serial Interface Control Registers COM1 Addr. 3F8h COM2 Addr. 2F8h 3F9h 2F9h 3FAh 2FAh 3FBh 2FBh 3FCh 2FCh 3FDh 2FDh 3FEh 2FEh Register Receive Data Buffer Transmit Data Buffer Baud Rate Divisor Register 0 (when bit 7 of Line Control Reg. Is set) Baud Rate Divisor Register 1 (when bit 7 of Line Control Reg. Is set) Interrupt Enable Register: <7..
Chapter 5 Input/Output Interfaces 5.5 PARALLEL INTERFACE The legacy-light models include a parallel interface for connection to a peripheral device that has a compatible interface, the most common being a printer. The parallel interface function is integrated into theLPC47B277 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device.
Technical Reference Guide 5.5.2 ENHANCED PARALLEL PORT MODE In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If compatible, then EPP mode can be used.
Chapter 5 Input/Output Interfaces 5.5.4 PARALLEL INTERFACE PROGRAMMING Programming the parallel interface consists of configuration, which typically occurs during POST, and control, which occurs during runtime. 5.5.4.1 Parallel Interface Configuration The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also must be enabled before it can be used. When configured for EPP or ECP mode, additional considerations must be taken into account.
Technical Reference Guide 5.5.4.2 Parallel Interface Control The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17. The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP).
Chapter 5 Input/Output Interfaces Status Register, I/O Port 379h, Read Only This register contains the current printer status. Reading this register clears the interrupt condition of the parallel port.
Technical Reference Guide FIFO Register, I/O Port 7F8h (ECP Mode Only) While in ECP/forward mode, this location is used for filling the 16-byte FIFO with data bytes. Reads have no effect (except when used in Test mode). While in ECP/backward mode, reads yield data bytes from the FIFO. Configuration Register A, I/O Port 7F8h (ECP Mode Only) A read of this location yields 10h, while writes have no effect.
Chapter 5 Input/Output Interfaces 5.5.5 PARALLEL INTERFACE CONNECTOR Figure 5-5 and Table 5-10 show the connector and pinout of the parallel interface connector. Note that some signals are redefined depending on the port’s operational mode. Figure 5-5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis) Table 5–10. DB-25 Parallel Connector Pinout Table 5-10.
Technical Reference Guide 5.6 KEYBOARD/POINTING DEVICE INTERFACE The legacy-light models include PS/2-type keyboard/pointing device interfaces for the connection of a standard enhanced keyboard and a mouse. (Legacy-free models use USB ports for keyboard/mouse connections.
Chapter 5 Input/Output Interfaces Control of the data and clock signals is shared by the 8042and the keyboard depending on the originator of the transferred data. Note that the clock signal is always generated by the keyboard. After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a parity error or timeout occurs, a Resend command is sent to the 8042. Table 5-11 lists and describes commands that can be issued by the 8042 to the keyboard. Table 5–11.
Technical Reference Guide 5.6.2 POINTING DEVICE INTERFACE OPERATION The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical to the keyboard connector both physically and electrically. The operation of the interface (clock and data signal control) is the same as for the keyboard. The pointing device interface uses the IRQ12 interrupt. 5.6.
Chapter 5 Input/Output Interfaces 5.6.3.2 8042 Control The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Subfunctions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the keyboard’s scan codes into ASCII codes).
Technical Reference Guide Table 5-13 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for gaining the attention of the CPU. Table 5–13. CPU Commands To The 8042 Table 5-13. CPU Commands To The 8042 Value 20h 60h A4h A5h A6h A7h A8h A9h AAh ABh ADh AEh Command Description Put current command byte in port 60h. Load new command byte. This is a two-byte operation described as follows: 1. Write 60h to port 64h. 2.
Chapter 5 Input/Output Interfaces Table 5-13. CPU Commands To The 8042 (Continued) Value C0h C2h C3h D0h D1h D2h D3h D4h E0h F0hFFh Command Description Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port to the output buffer so that they can be read at port 60h.
Technical Reference Guide 5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device. Both connectors are identical both physically and electrically. Figure 5-7 and Table 5-14 show the connector and pinout of the keyboard/pointing device interface connectors. Figure 5-7. Keyboard or Pointing Device Interface Connector (as viewed from rear of chassis) Table 5–14. Keyboard/Pointing Device Connector Pinout Table 5-17.
Chapter 5 Input/Output Interfaces 5.7 UNIVERSAL SERIAL BUS INTERFACE The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers of up to 12 Mb/s with compatible peripherals such as keyboards, printers, or modems. This high-speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems.
Technical Reference Guide The USB transmissions consist of packets using one of four types of formats (Figure 5-9) that include two or more of seven field types. ♦ Sync Field – 8-bit field that starts every packet and is used by the receiver to align the incoming signal with the local clock. ♦ Packet Identifier (PID) Field – 8-bit field sent with every packet to identify the attributes (in.
Chapter 5 Input/Output Interfaces 5.7.2 USB PROGRAMMING Programming the USB interface consists of configuration, which typically occurs during POST, and control, which occurs at runtime. 5.7.2.1 USB Configuration The USB interface functions as a PCI device (31) within the 82801 component (function 2) and is configured using PCI Configuration Registers as listed in Table 5-15. Table 5–15. USB Interface Configuration Registers Table 5-15. USB Interface Configuration Registers PCI Config. Addr.
Technical Reference Guide 5.7.3 USB CONNECTOR The USB interface provides two series-A connectors on the front panel and, on legacy-free models, three series-A USB connectors on the rear panel. 1 2 3 4 Figure 5-10. Universal Serial Bus Connector Table 5–17. USB Connector Pinout Table 5-17. USB Connector Pinout Pin 1 2 Signal Vcc USB- Description +5 VDC Data (minus) Pin 3 4 Signal USB+ GND Description Data (plus) Ground 5.7.
Chapter 5 Input/Output Interfaces 5.8 AUDIO SUBSYSTEM A PCI audio subsystem is integrated onto the system board of the Compaq iPAQ. Implementing AC’97 design guidelines, the audio subsystem is designed to provide optimum sound. Key features of the audio subsystem include: ♦ ♦ ♦ ♦ ♦ ♦ AC’97 ver. 2.1 compliance Multiple audio channel streaming Soft CD, DVD/AC-3 processing Wavetable synthesis utilizing system memory Acoustic echo cancellation 16-bit stereo PCM input and output w/ up to 48 KHz sampling 5.8.
Technical Reference Guide 82801 ICH PC Beep Audio Reset PCI Bus SD OUT AC’97 Audio Cntlr. SD IN SYNC BIT_CLK AC97 Link Bus Mic In Audio Bias Internal Speaker (L) Line In (R) AD1881 Audio Codec PB Audio (L/R) TDA 7056 + - CD Audio (L) CD ROM CD Audio (R) (L) (R) (L) (R) Line Out Headphones Out Figure 5-11.
Chapter 5 Input/Output Interfaces 5.8.2 AC97 AUDIO CONTROLLER The AC97 Audio Controller is a PCI device (device 31/function 5) that is integrated into the 82801 ICH component and supports the following functions: ♦ ♦ ♦ ♦ ♦ ♦ Read/write access to audio codec registers 16-bit stereo PCM output @ up to 48 KHz sampling 16-bit stereo PCM input @ up to 48 KHz sampling Acoustic echo correction for microphone AC’97 Link Bus ACPI power management 5.8.
Technical Reference Guide 5.8.4 AUDIO CODEC The audio codec provides pulse code modulation (PCM) coding and decoding of audio information as well as the selection and/or mixing of analog channels. As shown in Figure 5-13, analog audio from a microphone, tape, or CD can be selected and, if to be recorded (saved) onto a disk drive, routed through an analog-to-digital converter (ADC).
Chapter 5 Input/Output Interfaces 5.8.5 AUDIO PROGRAMMING Audio subsystem programming consists configuration, typically accomplished during POST, and control, which occurs during runtime. The register maps are described in the following subsections. 5.8.5.1 Audio Configuration The audio subsystem is configured according to PCI protocol through the AC’97 audio controller function of the 82801 ICH. Table 5-19 lists the PCI configuration registers of the audio subsystem. Table 5–19.
Technical Reference Guide 5.8.6 AUDIO SPECIFICATIONS The specifications of the audio subsystem are listed in Table 5-21. Table 5–21. Audio Subsystem Specifications Table 5-21. Audio Subsystem Specifications Paramemter Sampling Rate Resolution Nominal Input Voltage: Mic In (w/+20 db gain Line In Impedance: Mic In Line In Line Out Signal-to-Noise Ratio (input to Line Out) Max. Power Output (into 8 ohms) Total Harmonic Distortion (THD) (to int. spkr): @ 0.5 watts @ max.
Chapter 5 Input/Output Interfaces 5.9 NETWORK INTERFACE CONTROLLER The Compaq iPAQ includes a network interface controller (NIC) resident on the system board. The NIC (Figure 5-14) includes the 82559 controller, two LED indicators, and support firmware. The support firmware is contained in the system (BIOS) ROM. The NIC can operate in half- or full-duplex modes, and provides auto-negotiation of both mode and speed.
Technical Reference Guide NOTE: For the WOL and AOL features to function as described in the following paragraphs, the system unit must be plugged into a live AC outlet. Controlling unit power through a switchable power strip will, with the strip turned off, disable WOL and AOL functionality. 5.9.
Chapter 5 Input/Output Interfaces 5.9.3 POWER MANAGEMENT SUPPORT The 82559 controller features Wired-for-Management (WfM) support providing system wake up from network events (WOL) as well as generating system status messages (AOL) and supports both APM and ACPI power management environments. The controller receives 3.
Technical Reference Guide 5.9.4 NIC PROGRAMMING Programming the 82559 NIC controller consists of configuration, which occurs during POST, and control, which occurs at runtime. 5.9.4.1 Configuration The 82559 controller is a PCI device and configured though PCI configuration space registers using PCI protocol described in chapter 4. The PCI configuration registers are listed in the following table: Table 5–23. NIC Controller PCI Configuration Registers Table 5-23.
Chapter 5 Input/Output Interfaces 5.9.4.3 RJ-45 Connector Figure 5-15 shows the RJ-45 connector used for the NIC interface. This connector includes the two status LEDs as part of the connector assembly. Activity LED Speed LED Pin 1 2 3 6 Description Transmit+ TransmitReceive+ Receive- 8 7 6 5 4 3 2 1 Figure 5-15. Ethernet TPE Connector (RJ-45, viewed from card edge) 5.9.4.4 82559 NIC Specifications Table 5–25. 82559 NIC Operating Specifications Table 5-25.
Technical Reference Guide Chapter 6 GRAPHICS SUBSYSTEM 6. Chapter 6 Graphics Subsystem 6.1 INTRODUCTION This chapter describes the graphics subsystem of the Compaq iPAQ Internet Device. The 82810e/DC-100 GMCH component integrates the equivalent of the Intel i740 graphics controller, which employs the AGP interface allowing the use of system memory to provide efficient, economical 2D and 3D performance. This chapter covers the following subjects: ♦ ♦ ♦ ♦ ♦ ♦ Functional description (6.
Chapter 6 Graphics Subsystem 6.2 FUNCTIONAL DESCRIPTION The Intel 810e chipset integrates the equivalent of an Intel i740 graphics controller into the GMCH component (Figure 6-1). 82810e/DC-100 GMCH FSB I/F 4 MB SDRAM Display Cache Monitor RGB i740 Graphics Controller SDRAM Controller Hub Link I/F Pentium III-based system only. Figure 6-1.
Technical Reference Guide 82810e/DC-100 GMCH i740-Equiv. Graphics Controller 4 MB SDRAM Display Cache DC I/F 2D Engine 3D Engine HSync Monitor Connector HSync RGB RAM DAC Pipelined Preprocessor AGP I/F FSB I/F & SDRAM Cntlr. Pentium III-based system only. Figure 6-2. 82810e/DC-100 Integrated Graphics Controller The Intel graphics controller includes special enhancements for 2D operations. Motion compensation logic is included to improve performance during software decoding of MPEG2 video.
Chapter 6 Graphics Subsystem 6.3 DISPLAY MODES The Intel graphics controller supports the following 2D display modes: Table 6-1. Intel Graphics Display Modes Table 6-1.
Technical Reference Guide 6.5 PROGRAMMING 6.5.1 CONFIGURATION The graphics subsystem works off the AGP bus and is configured through PCI configuration space registers using PCI protocol. These registers (Table 6-3) are configured by BIOS during POST. Table 6-2. PCI Configuration Space Registers Table 6-3. PCI Configuration Space Registers PCI Config. Address 00h 04h 08h 10h Function Vender ID/Device ID PCI Command Status Display Memory Base Address PCI Config.
Chapter 6 Graphics Subsystem 6.6 MONITOR POWER MANAGEMENT CONTROL This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table 6-5 lists the monitor power conditions. Table 6-4. Monitor Power Management Conditions Table 6-5. Monitor Power Management Conditions 6.
Technical Reference Guide Chapter 7 POWER and SIGNAL DISTRIBUTION 7. Chapter 7 POWER SUPPLY AND DISTRIBUTION 7.1 INTRODUCTION This chapter describes the power supply and method of general power and signal distribution. Topics covered in this chapter include: ♦ ♦ ♦ 7.2 Power supply assembly/control (7.2) Power distribution (7.3) Signal distribution (7.
Chapter 7 Power and Signal Distribution 7.2.1 POWER SUPPLY ASSEMBLY The power supply assembly is contained in a single unit that features a selectable input voltage: 90-132 VAC and 180-264 VAC. The system uses a 90-watt supply with specifications listed in Table 7-1. Table 7–1. 90-Watt Power Supply Assembly Specifications Table 7-1. 90-Watt Power Supply Assembly Specifications (P/N 159447) Range/ Tolerance Min. Current Loading [1] Max.
Technical Reference Guide 7.2.2 POWER CONTROL The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When PS On is de-asserted, the Power Supply Assembly is off and no voltages (except +5 AUX) are generated. Note that the +5 AUX voltage is always produced as long as the system is connected to a live AC source.
Chapter 7 Power and Signal Distribution 7.3 POWER DISTRIBUTION 7.3.1 3.3/5/12 VDC DISTRIBUTION The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5 VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the individual drive assemblies. Figure 7-2 shows the power supply cabling. P3 P3 1 Power Supply Assembly (SP# 159447) 2 3 4 P1 P1 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 Conn. # Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 P1 +3.3 +3.
Technical Reference Guide 7.4 SIGNAL DISTRIBUTION Figures 7-4 shows general signal distribution between the main subassemblies of the system unit. PWR Btn Conn J8C1 Power ButtonLED Board (PCA# 010647) PWR LED HD LED Mic Audio In Conn J2D1 HP Audio Out Audio-USB I/F Board (PCA# 010650) Line Out Audio USB Tx/Rx 3 Conn J7A1 Conn J8B1 USB Tx/Rx 4 +3.5, +/- 5, +/- 12 VDC Power Supply Assembly System Board (PCA # 161014 or 161015) Pri. IDE J7E1 Sec.
Chapter 7 Power and Signal Distribution Audio Header J2D1 Power Button/LED Header J8C1 HD LED + 1 2 Pwr LED + HD LED - 3 Gnd 5 4 NC 6 Pwr Btn Reset 7 Mic Audio 1 Mic Bias 3 Gnd 5 10 ICH Service NC 11 HP Audio L 7 8 Line Audio R 10 HP Audio R 12 Gnd Gnd 13 NC 15 16 NC +5 Vcc 17 Not implemented USB Header J7A2 Gnd 1 2 Gnd Port 3 Data + 3 +5 Vcc 5 4 Port 3 Data 6 +5 Vcc Port 4 Data + 7 8 Port 4 Data - Gnd 9 CD Audio Header P7 1 Ground 2 Audio (left channel) 3 Ground 4 Audio (right chann
Technical Reference Guide Chapter 8 BIOS ROM 8. Chapter 8 BIOS ROM 8.1 INTRODUCTION The Compaq iPAQ Internet Device uses Compaq BIOS firmware loaded into the 82802 FWH component. The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power management activities, and Setup. This chapter includes the following topics: ♦ ♦ ♦ ♦ ♦ ♦ Boot/reset functions (8.2) Memory detection and configuration (8.3) PnP support (8.5) Power management functions (8.
Chapter 8 BIOS ROM 8.2 DESKTOP MANAGEMENT SUPPORT Desktop Management deals with issues of security, identification, and system management functions. Desktop Management is provided by BIOS INT 15 functions listed Table 8-1. Table 8-1. Desktop Management Functions (INT15) Table 8-1.
Technical Reference Guide To support Windows NT an additional table to the BIOS32 table has been defined to contain 32bit pointers for the DDC and SIT locations.
Chapter 8 BIOS ROM 8.2.1 SYSTEM ID The INT 15, AX=E800h BIOS function can be used to identify the type of system. This function will return the system ID in the BX register. System Compaq iPAQ ROM Type 686J1 PnP ID CPQB1A0 System ID 0630h 8.2.2 SYSTEM INFORMATION TABLE The System Information Table (SIT) is a comprehensive list of fixed configuration information arranged into records. The INT 15 AX=E807h BIOS function accesses the SIT by returning a pointer in ES:BX to indicate the location of the SIT.
Technical Reference Guide 8.2.3 EDID RETRIEVE The BIOS function INT 15, AX=E813h is a tri-modal call that retrieves the VESA extended display identification data (EDID). Two subfunctions are provided: AX=E813h BH=00h retrieves the EDID information while AX=E813h BX=01h determines the level of DDC support. Input: AX BH BH = E813h = 00 Get EDID .
Chapter 8 BIOS ROM 8.2.5 SYSTEM MAP RETRIEVAL The BIOS function INT 15, AX=E820h will return base memory and ISA/PCI memory contiguous with base memory as normal memory ranges. This real mode call will indicate chipset-defined address holes that are not in use, motherboard memory-mapped devices, and all occurrences of the system BIOS as reserved. Standard PC address ranges will not be reported.
Technical Reference Guide 8.2.6 FLASH ROM FUNCTIONS The system BIOS may be upgraded by flashing the ROM using the INT 15, AX=E822h BIOS interface, which includes the necessary subfunctions. An upgrade utility is provided on a ROMPAQ diskette. 8.2.7 POWER BUTTON FUNCTIONS The BIOS includes an interface for controlling the system unit’s power button. The power button can be disabled and enabled.
Chapter 8 BIOS ROM 8.2.8 ACCESSING CMOS Configuration memory data can be retrieved with the BIOS call INT 15, AX=E823h. This trimodal function retrieves a specific byte from the CMOS map described in Chapter 4.
Technical Reference Guide Table 8-2. CMOS Feature Bits Table 8-2. CMOS Feature Bits CX 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h NOTE: Function PCI 2.1 Mode Enable Erase Eaze Kybd COM/IR Port Select PnP Rejects SET PCI VGA Snoop PCI Bus Mastering Auto Prompt Setup Mode 2 Config. Enable Sec. IDE Cntlr, En. Sec. IDE Cntlr.
Chapter 8 BIOS ROM 8.2.10 SECURITY FUNCTIONS The INT 15 AX=E846h BIOS function is used to control various security features of the system. This function may be issued by a remote system (over a network). The issuing driver must build a request buffer for each security feature prior to making the call.
Technical Reference Guide 8.3 MEMORY DETECTION AND CONFIGURATION This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM configuration. The BIOS communicates with an EEPROM on each DIMM through an I2C-type bus to obtain data on the following DIMM parameters: ♦ ♦ ♦ ♦ Presence Size Type Timing/CAS latency NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and DIMM data specific to this system.
Chapter 8 BIOS ROM 8.4 PNP SUPPORT The BIOS includes Plug ’n Play (PnP) support for PnP version 1.0A. NOTE: For full PnP functionality to be realized, all peripherals used in the system must be designed as “PnP ready.” Any installed ISA peripherals that are not “PnP ready” can still be used in the system, although configuration parameters may need to be considered (and require intervention) by the user.
Technical Reference Guide 8.4.1 SMBIOS This system supports System Management BIOS (SMBIOS) version 2.3.1, which is compliant with the Desktop Management Interface (DMI) specification. The PnP functions 50h and 51h are used to retrieve the SMBIOS data, which is stored using management information format (MIF) structures. Function 50h retrieves the number of structures, size of the largest structure, and SMBIOS version. Function 51h retrieves a specific structure.
Chapter 8 BIOS ROM 8.5 POWER MANAGEMENT FUNCTIONS The BIOS provides three types of power management support: independent PM support; ACPI support, and APM support. These power management interfaces share a common goal of reducing energy consumption during periods of system inactivity. The following table compares and describes the different system states identified by the various power management interfaces. Global State G0 Sleep State -- G1 S1 S2/S3 S4 G2 S5 G3 -- System Condition Fully on.
Technical Reference Guide 8.5.2 ACPI SUPPORT This system meets the hardware and firmware requirements for being ACPI compliant. The BIOS function INT 15 AX=E845h can be used to check or set the ACPI enable/disable status of the system, which defaults to the “ACPI enabled” state. The setup option for ACPI should be disabled if APM/PnP is to be used with Windows 98 or when disabling power management and PnP support for NT5.0.
Chapter 8 BIOS ROM Three power states are defined under power management: On - The computer is running, all subsystems are on and drawing full power. Any activity in the following subsystems will reset the activity timer, which has a default setting of 15 minutes before Standby entered: a. Keyboard (PS/2 only) b. Mouse (PS/2 only) c. Serial port d.
Technical Reference Guide The APM BIOS for this system supports APM 1.2 as well as previous versions 1.1 and 1.0. The APM BIOS functions are listed in Table 8-3. Table 8-4. APM BIOS Functions (INT15) Table 8-3. APM BIOS Functions (INT15) AX 5300h 5301h 5302h 5303h 5304h 5305h 5306h 5307h 5308h 5309h 530Ah 530Bh 530Ch 530Dh 530Eh 530Fh 5380h 8.
Chapter 8 BIOS ROM 8.7 BIOS UPGRADING The flash ROM device can be re-written with updated BIOS code if necessary. The flashing procedure is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Create a system (bootable) diskette using the FORMAT A: /S command in DOS. Download the appropriate BIOS firmware from the Compaq web site. Copy the downloaded BIOS file and the flash utility file onto the boot diskette. Unzip the BIOS and flash utility files, which should result in an .exe file and a .
Technical Reference Guide Appendix A ERROR MESSAGES AND CODES A. Appendix A ERROR MESSAGES AND CODES A.1 INTRODUCTION This appendix lists the error codes and a brief description of the probable cause of the error. Note that not all errors listed in this appendix may be applicable to a particular system depending on the model and/or configuration. A.2 POWER-ON MESSAGES Table A–1. Power-On Messages Table A-1. Power-On Messages Message CMOS Time and Date Not Set (none) Run Setup A.
Appendix A Error Messages and Codes A.4 POWER-ON SELF TEST (POST) MESSAGES Table A–3. Power-On Self Test (POST) Messages Table A-3.
Technical Reference Guide A.5 PROCESSOR ERROR MESSAGES (1xx-xx) Table A–4. System Error Messages Table A-4. System Error Messages Message 101 102 103 104-01 104-02 104-03 105-01 105-02 105-03 105-04 105-05 105-06 105-07 105-08 105-09 105-10 105-11 105-12 105-13 105-14 106-01 107-01 108-02 108-03 109-01 109-02 109-03 Probable Cause Option ROM error System board failure (see note) System board failure Master int. cntlr. test fialed Slave int. cntlr. test failed Int. cntlr.
Appendix A Error Messages and Codes A.6 MEMORY ERROR MESSAGES (2xx-xx) Table A–5. Memory Error Messages Table A-5. Memory Error Messages Message 200-04 200-05 200-06 200-07 200-08 201-01 202-01 202-02 202-03 203-01 203-02 203-03 204-01 204-02 204-03 204-04 204-05 205-01 205-02 205-03 206-xx 207-xx 210-01 210-02 210-03 211-01 211-02 211-03 213-xx 214-xx 215-xx A.
Technical Reference Guide A.8 PRINTER ERROR MESSAGES (4xx-xx) Table A–7. Printer Error Messages Table A-7. Printer Error Messages Message 401-01 402-01 402-02 402-03 402-04 402-05 402-06 402-07 402-08 402-09 402-10 A.9 Probable Cause Printer failed or not connected Printer data register failed Printer control register failed Data and control registers failed Loopback test failed Loopback test and data reg. failed Loopback test and cntrl. reg. failed Loopback tst, data/cntrl. reg.
Appendix A Error Messages and Codes A.10 DISKETTE DRIVE ERROR MESSAGES (6xx-xx) Table A–9. Diskette Drive Error Messages Table A-9.
Technical Reference Guide A.12 MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx) Table A–11. Serial Interface Error Messages Table A-11.
Appendix A Error Messages and Codes A.13 SYSTEM STATUS ERROR MESSAGES (16xx-xx) Table A–12. System Status Error Messages Table A-12. System Status Error Messages Message Probable Cause 1601-xx Temperature violation 1611-xx Fan failure See Table A-18 for additional messages. A.14 HARD DRIVE ERROR MESSAGES (17xx-xx) Table A–13. Hard Drive Error Messages Table A-13. Hard Drive Error Messages Message Probable Cause 17xx-01 Exceeded max. soft error limit 17xx-02 Exceeded max.
Technical Reference Guide A.15 HARD DRIVE ERROR MESSAGES (19xx-xx) Table A–14. Hard Drive Error Messages Table A-14.
Appendix A Error Messages and Codes A.17 AUDIO ERROR MESSAGES (3206-xx) Table A–16. Audio Error Messages Table A-16. Audio Error Message Message 3206-xx Probable Cause Audio subsystem internal error A.18 DVD/CD-ROM ERROR MESSAGES (33xx-xx) Table A–17. DVD/CD-ROM Drive Error Messages Table A-17. DVD/CD-ROM Drive Error Messages Message Probable Cause 3301-xx Drive test failed 3305-XX Seek test failed See Table A-18 for additional messages. A.19 NETWORK INTERFACE ERROR MESSAGES (60xx-xx) Table A–18.
Technical Reference Guide A.20 SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx) Table A–19. SCSI Interface Error Messages Table A-19.
Appendix A Error Messages and Codes A.22 CEMM PRIVILEDGED OPS ERROR MESSAGES Table A–21. CEMM Privileged Ops Error Messages Table A-21. CEMM Privileged Ops Error Messages Message 00 01 02 03 Probable Cause LGDT instruction LIDT instruction LMSW instruction LL2 instruction Message 04 05 06 07 Probable Cause LL3 instruction MOV CRx instruction MOV DRx instruction MOV TRx instruction A.23 CEMM EXCEPTION ERROR MESSAGES Table A–22. CEMM Exception Error Messages Table A-22.
Technical Reference Guide Appendix B ASCII CHARACTER SET B. Appendix B ASCII CHARACTER SET B.1 INTRODUCTION This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard textmode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol.
Appendix B ASCII Character Set Table B-1. ASCII Code Set (Continued) Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol Ç á J .
Technical Reference Guide Appendix C KEYBOARD C. Appendix C KEYBOARD C.1 INTRODUCTION This appendix describes the Compaq keyboard that is included as standard with the system unit. The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions. This appendix covers the following keyboard types: ♦ Standard enhanced keyboard.
Appendix C Keyboard C.2 KEYSTROKE PROCESSING A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power (+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms for pressed keys while at the same time monitoring communications with the keyboard interface of the system unit. When a key is pressed, a Make code is generated.
Technical Reference Guide C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS The PS/2-type keyboard sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system (specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and loads the data into a buffer.
Appendix C Keyboard C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS The USB-type keyboard sends essentially the same information to the system that the PS/2 keyboard does, except that the data receives additional NRZI encoding and formatting (prior to leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this guide). Packets received at the system’s USB I/F and decoded as originating from the keyboard result in an SMI being generated.
Technical Reference Guide C.2.3 KEYBOARD LAYOUTS Figures C-3 through C-8 show the key layouts for keyboards shipped with Compaq systems. Actual styling details including location of the Compaq logo as well as the numbers lock, caps lock, and scroll lock LEDs may vary. C.2.3.
Appendix C Keyboard C.2.3.2 Windows Enhanced Keyboards 1 18 17 2 3 4 5 19 20 21 22 40 39 59 60 75 92 41 42 61 76 43 62 77 6 23 44 63 78 24 45 64 79 8 25 46 65 80 93 110 7 26 47 66 81 9 27 48 67 82 94 11 28 29 50 49 68 83 10 95 13 31 30 51 70 69 84 12 14 15 16 32 33 34 35 36 37 52 53 54 55 56 57 72 73 74 88 89 90 71 85 87 86 96 111 112 97 98 99 100 38 58 91 101 Figure C–5. U.S.
Technical Reference Guide C.2.3.3 Easy Access Keyboards The Easy Access keyboard, such as that shipped with the Compaq iPaq system, is a Windows Enhanced-type keyboard that includes special buttons (Figure C-7) allowing quick internet navigation. Depending on the system, either a legacy PS/2-type keyboard or a Universal Serial Bus (USB) type keyboard may be employed. Either type uses the layout shown in the following figure.
Appendix C Keyboard C.2.4 KEYS All keys generate a make code (when pressed) and a break code (when released) with the exception of the Pause key (pos. 16), which produces a make code only. All keys with the exception of the Pause and Easy Access keys are also typematic, although the typematic action of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the BIOS.
Technical Reference Guide C.2.4.2 Multi-Keystroke Functions Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower (normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of key positions 55-57, 72, 74, 88-90, 100, and 101.
Appendix C Keyboard C.2.4.4 Easy Access Keystrokes The Easy Access keyboard (Figure C-7) includes additional keys (also referred to as buttons) used to streamline internet navigation.
Technical Reference Guide C.2.5 KEYBOARD COMMANDS Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042type logic). Table C–1. Keyboard-to-System Commands Table C-1. Keyboard-to-System Commands Command Key Detection Error/Over/run BAT Completion BAT Failure Echo Acknowledge (ACK) Resend Keyboard ID Value 00h [1] FFh [2] AAh FCh EEh FAh FEh 83ABh Description Indicates to the system that a switch closure couldn’t be identified.
Appendix C Keyboard Table C–2. Keyboard Scan Codes Table C-2. Keyboard Scan Codes Key Pos.
Technical Reference Guide Table C-2.
Appendix C Keyboard Table C-2. Keyboard Scan Codes (Continued) Key Pos. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Legend N M , . / Shift (right) 1 2 3 Enter Ctrl (left) Alt (left) (Space) Alt (right) Ctrl (right) 98 99 100 101 102 103 104 110 0 .
Technical Reference Guide C.3 CONNECTORS Two types of keyboard interfaces are used in Compaq systems: PS/2-type and USB-type. Systems that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will ship with a USB keyboard. For a detailed description of the PS/2 and USB interfaces refer to the Input/Output chapter of this guide.
Appendix C Keyboard This page is intentionally blank.
INDEX I.
key (keyboard) functions, C-8 keyboard, C-1 keyboard (micro)processor, C-2 keyboard layouts, C-5 keyboard, USB, C-4 keyboard/pointing device interface, 5-15 keys, Easy Access, C-10 low voltages, 7-4 LPC bus, 4-6 Magic Packet, 5-34 mass storage, 2-14 media write protect function (BIOS), 8-10 memory detection, 8-11 memory map, 3-7 memory, system, 3-5 memory, system (RAM), 2-13 MMX, 3-2 monitor power control, 6-6 motherboard, 2-7 mouse interface, 5-17 MultiBay, 2-14 network interface controller (NIC), 5-33 net
