FreeForm/PCI-104 User Manual Connect Tech, Inc. 42 Arrow Road Guelph, Ontario Canada, N1K 1S6 Tel: 519-836-1291 800-426-8979 Fax: 519-836-4878 Email: sales@connecttech.com support@connecttech.com URL: http://www.connecttech.com CTIM-00040 Revision 0.
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Connect Tech FreeForm/PCI-104 User Manual Table of Contents Limited Lifetime Warranty......................................................................................................... 2 Copyright Notice ........................................................................................................................ 2 Trademark Acknowledgment ..................................................................................................... 2 Customer Support Overview .......................
Connect Tech FreeForm/PCI-104 User Manual List of Tables Table 1: FreeForm/PCI-104 Components .................................................................................. 7 Table 2: Slot Selection (RSW1) ................................................................................................. 8 Table 3: FPGA Configuration Settings (J1) ............................................................................... 8 Table 4: JTAG Programming Header Pinout (P2).................................
Connect Tech FreeForm/PCI-104 User Manual Introduction Connect Tech’s FreeForm/PCI-104 features Xilinx’s Virtex-5 multi-platform FPGA offering users a flexible, reconfigurable product that also takes advantage of the high bandwidth capabilities of the PCI bus while communicating with various I/O interfaces.
Connect Tech FreeForm/PCI-104 User Manual Figure 2: FreeForm/PCI-104 Layout Table 1: FreeForm/PCI-104 Components Connectors P1 P2 P3 P5, P6 P7 P8 P9 P10 Jumpers /Switches RSW1 J1 Components D1-D4 D5 U4 U5 U10 U11 U12, U13 U14 U15, U16 U17 O1 Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Hardware Description and Configuration The following sections describe the function of all switches/jumpers and provide details on connector pinouts. Jumpers and Switches Slot Selection (RSW1) This rotary switch selects a slot position in the PCI-104 stack. When mounting on a PCI adapter card, ensure slot one is selected.
Connect Tech FreeForm/PCI-104 User Manual Connector Pinouts PCI-104 Header (P1) Refer to PCI-104 specifications. Note: P1 must be connected to a PCI-104 stack supplying both 3.3V and 5V JTAG Programming Header (P2) Use P2 to configure the FPGA via JTAG. Refer to Programming the FPGA for more information. Power pins are for voltage reference only; they do not provide power to the configuration circuitry. Note that the FPGA can always be programmed via JTAG, regardless of the J1 configuration setting.
Connect Tech FreeForm/PCI-104 User Manual RS-485 Headers (P5, P6) Table 6: RS-485 Port 1 Pinout (P5) Table 7: RS-485 Port 2 Pinout (P6) Pin 1 2 3 4 5 6 7 8 9 10 Pin 1 2 3 4 5 6 7 8 9 10 Signal RXD+1 Direction Input RXD-1 Input TXD+1 Output TXD-1 Output GND power Signal RXD+2 Direction Input RXD-2 Input TXD+2 Output TXD-2 Output GND power External Power Connector (P8) The external connector provides 5V to the power regulation circuitry. In addition, the power connector enables the 3.
Connect Tech FreeForm/PCI-104 User Manual GPIO Header (P7) The GPIO header has been design such that when in differential mode, the positive (P) and negative (N) signals are adjacent on a standard ribbon cable. Note that the GPIO voltage level is set via hardware. FCG001: has L12 populated, enabling 2.5V I/O, including LVDS FCG002: has L13 populated, enabling 3.3V I/O Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Hardware Installation Before installing the FreeForm/PCI-104 into a PC/104 stack, ensure the following: o o Slot selection properly set using the rotary switch RSW1. Note that the FreeForm/PCI-104 address space consumes 32 bytes. FPGA configuration jumper J1 is set to read from Flash Once installed in the system and power is applied, the LED D1 will illuminate to indicate that FreeForm/PCI-104 is functioning properly.
Connect Tech FreeForm/PCI-104 User Manual FPGA Configuration To configure the FPGA via JTAG, connect the JTAG programming cable to P2 ensuring that all JTAG signals align correctly. It is important to note that P2 also has the TRST signal on pin 1, which is not part of Xilinx’s Parallel or USB programming cables. Launch Impact 1) Open iMPACT, and select create a new project 2) Select configure devices using boundary scan. iMPACT will scan the JTAG chain, and identify three devices.
Connect Tech FreeForm/PCI-104 User Manual 3) A prompt will ask for a new configuration file. Select the bitstream from the project directory. 4) A prompt will ask for a BSDL file for device number 2 (PLX PCI9056). Click Yes. 5) Browse to the bsdl folder and select PCI9056BA.bsd Revision 0.
Connect Tech FreeForm/PCI-104 User Manual 6) iMPACT will add the device to the JTAG chain. 7) Again, a prompt will ask for device number three (National PHY). Browse to the bsdl folder and select DP83849IVS.bsd. The device will be added to the JTAG chain. 8) To test stream integrity, right click on the FPGA and select Get Device ID. The console will report IDCODE = 82a6e093 Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Programming the FPGA 1) Right click on device number one (Virtex-5 FPGA), and select program. The following diagram will appear. Note that verification will only work if an msk file has been created. 2) Select OK to begin programming. After programming is complete, the status window will report: Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Generating a PROM (MCS) File 1) Double click Prom File Formatter in the Flows window. 2) The “Prepare PROM Files” dialog will appear. Ensure that the following settings are selected: 3rd Party SPI PROM MSC PROM File Format 3) Give the file a name, and click Next. Revision 0.
Connect Tech FreeForm/PCI-104 User Manual 4) Select the PROM density (16M) → click Next → click Finish. 5) A prompt will ask to add device to data stream 0. Click OK. Select the bitstream from the project directory. Revision 0.
Connect Tech FreeForm/PCI-104 User Manual 6) Click “No” when asked if another device is to be added. Click “OK” to accept the setup. 7) Double Click “Generate File” from the “iMPACT” processes menu. The status will be reported in the console.
Connect Tech FreeForm/PCI-104 User Manual Configuring the FPGA with the SPI Flash In previous Xilinx FPGA configurations, the SPI flash would require programming via 3rd party JTAG test software or through in-system methods. The following features are new to ISE 9.1/9.2, and are only available on select FPGAs, including the Virtex-5. Your FreeForm/PCI-104 card featuring the Xilinx Virtex-5 FPGA includes a standard core to enable programming of BPI and SPI flashes over JTAG.
Connect Tech FreeForm/PCI-104 User Manual 3) Browse to the directory containing the previously generated MCS file. Select and click “Open”. 4) The “FPGA SPI Flash Association” window will appear; select “M25P16” (this is the flash device connected to the FPGA). 5) The flash will be added to the FPGA. Note that this flash is not part of the JTAG chain. Revision 0.
Connect Tech FreeForm/PCI-104 User Manual Programming the Flash 1) Right click the previously associated flash device, and select program. 2) The programming dialog will appear. Select “Verify” and “Erase Before Programming”, then click OK. Revision 0.
Connect Tech FreeForm/PCI-104 User Manual 3) Observe the results in the transcript window. a. The SPI core is first download to the FPGA device b. The IDCODE is checked and verified c. Flash is erased d. Flash is programmed After completion of the flash programming, the FPGA will attempt to configure itself from the flash. If the SPI flash setting is not selected with J1; this step will fail. This does not mean the flash is not programmed, but rather the verification of the programmed contents has failed.
Connect Tech FreeForm/PCI-104 User Manual Reference Design The FreeForm/PCI-104 ships with a pre-installed reference design. This reference design demonstrates how the FPGA interacts with the PLX 9056 PLX to local bus bridge. Functionality o o o o o o Local bus interface driven at 50MHz Slave access to: o BAR2: 16x32 bit control registers , 16x32 bit user memory o BAR3: SPI flash programming interface Master access to same 16x32 user memory as located in BAR2.
Connect Tech FreeForm/PCI-104 User Manual Table 11: Local Address Space 1 (Bar 3) Local Address Contents Access Description 10000000 SPI Command RW SPI controller command register, once command is written operation begins 10000004 SPI Parameters RW There are four parameters, each one byte - 0x04: Param0 - 0x05: Param1 - 0x06: Param2 - 0x07: Param3 10000008 SPI Status R SPI controller status register - Bit 0: Operation complete 1000000C SPI Result R There are four results, each one byte -
Connect Tech FreeForm/PCI-104 User Manual Specifications Programmable FPGA Virtex-5 FPGA LX30T Input Clock 100MHz Memory 8MB Flash, 128MB DDR2-400 General Purpose User I/O 64 single ended I/O 32 LVDS I/O Serial 2 x RS-485 Ethernet 2 x 10Base-T, 100Base-TX Operating Environment Storage Temperature: -65°C to 150°C Operating Temperature: 0°C to 70°C -40°C to 85°C Power Requirements (commercial) (industrial) +3.
