User manual

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Option <9> Independent Watchdog
This option allows the operator to test the watchdog circuit. The system watchdog circuit
is composed of the DS1306 chip, which sends periodic interrupt requests to the TT8v2, and a
hardware counter, which can restart the TT8v2 if the IRQ from the DS1306 is not acknowledged.
<1> Test Watchdog IRQ ( 2 seconds)
<2> Test Watchdog RESET (68 minutes)
<B> Bench Tests Menu
Selection ?
Figure G-34: Test System Watchdog
The watchdog test temporarily resets the DS1306 clock, the WDC, so that the time is
2 seconds before the regularly scheduled watchdog IRQ. The watchdog sends the IRQ when the
2 seconds have expired, the TT8v2 detects the interrupt and acknowledges it, and the system,
including the WDC, is returned to normal. Failures are detected and reported to the operator. An
example is shown next.
WDC rest
IRQ sent and
detected
System
restored to
normal
operating
condition
Initializing . . . done.
Waiting for IRQ (2 seconds) . . . IRQ detected.
Watchdog IRQ test complete.
Watchdog is functioning normally.
Figure G-35: Test Watchdog IRQ
The Watchdog test re-programs the watchdog IRQ pin on the TT8v2 so that interrupts
from the DS1306 will be ignored, resets the hardware counter to zero and transitions to low
power sleep. The counter re-boots the TT8v2 after 68 minutes (4096 seconds). The test will
“time out” after 70 minutes if there is no reset and can be stopped manually at any time by typing
[CTRL]-[C]. An example of an operator terminated test is shown next.
G-27