User`s manual

CYDAS UDR Library User’s Guide Counter Boards - CYQUAD Series
118
indicates the routing of the FLG pins depending on the value of PhxA and PhxB. The actual values of the
BADR2+9 register are shown below:
Register BADR2 + 9 D0-D6
PH2A
PH2B PH3A PH3B PH4A PH4B1/PH4B0 Value
Case 1: (4) 24-bit counters (1/2/3/4) 0 0 0 0 0 0,0 00
Case 2: (2) 48-bit counters (1-2/3/4) 1 1 0 0 1 1,0 53
Case 3: (1) 24-bit, (1) 72-bit (1/2-3-4) 0 0 1 1 1 0,1 3C
Case 4: (1) 96-bit counter (1-2-3-4) 1 1 1 1 1 0,1 3F
Defaults to 0x00 (no inter-counter connections).
Examples
Case 1: (4) 24-bit counters (1/2/3/4)
cbC7266Config(0,1,0,0,2,0,0,1,0)
cbC7266Config(0,2,0,0,2,0,0,1,0)
cbC7266Config(0,3,0,0,2,0,0,1,0)
cbC7266Config(0,4,0,0,2,0,0,1,0)
Case 2: (2) 48-bit counters (1-2/3-4)
cbC7266Config(0,1,0,0,2,0,0,3,0)
cbC7266Config(0,2,0,0,2,0,0,1,0)
cbC7266Config(0,3,0,0,2,0,0,3,0)
cbC7266Config(0,4,0,0,2,0,0,1,0)
Case 3: (1) 24-bit & (1) 72-bit counter (1/2-3-4)
cbC7266Config(0,1,0,0,2,0,0,1,0)
cbC7266Config(0,2,0,0,2,0,0,3,0)
cbC7266Config(0,3,0,0,2,0,0,3,0)
cbC7266Config(0,4,0,0,2,0,0,1,0)
Case 4: (1) 96-bit counter (1-2-3-4)
cbC7266Config(0,1,0,0,2,0,0,3,0)
cbC7266Config(0,2,0,0,2,0,0,3,0)
cbC7266Config(0,3,0,0,2,0,0,3,0)
cbC7266Config(0,4,0,0,2,0,0,1,0)
The actual value of
the BADR+9 register is not set until the cbCLoad()/CLoad() command is called.
Counter4 setting
Setting Counter4 to CARRYBORROW-UPDOWN is NOT VALID.
Counter Cascading Functional Diagram
1
0
1A
1B
2A
2B
PH2A
PH2A
PH3A
PH3A
PH4AB1/B0
PH4AB1/B0
FLG1
FLG2
FLG3
FLG4
1A
1B
2A
2B
3A
3A
3B
4A
4B
1
0
1
0
1
0
1
0
10
01
00
3B
4B
4A