User`s manual

CYDAS UDR Library User’s Guide Analog Input Boards - PCYDAS and PCCDAS 16 Series
63
RegNum: LOADREG1, LOADREG2, LOADREG3
Triggering
PC-Card Only
Trigger functions and methods supported
UDR:
cbSetTrigger()
UDR for .NET: SetTrigger()
Trigger argument values
TrigType TRIGPOSEDGE, TRIGNEGEDGE, GATEHIGH, GATELOW (All at A/D External trigger
input)
Hardware considerations
Pacing analog input
 Internal or external clock
 The packet size is 256 samples for PCYDAS & PCYDIO boards; 2048 samples for
PCCDAS & PCCDIO boards.
For
CONTINUOUS mode scans, the sample count should be at least one packet size (>=2048 samples) for
the PCCDAS & PCCDIO boards.
These cards do not have residual counters, so
BLOCKIO transfers must acquire integer multiples of the packet
size before completing the scan. This can be lengthy for PCCDAS & PCCDIO, which must acquire 2048
samples between interrupts for
BLOCKIO transfers. In general, it is best to allow the library to determine the
best transfer mode (
SINGLEIO vs. BLOCKIO) for these boards.
Triggering and gating
 External digital (TTL) polled gate trigger supported on PCYDAS & PCYDIO versions. Refer to
"Trigger support
" on page 26.
 External digital (TTL) hardware trigger supported on PCCDAS & PCCDIO versions.