COMPACTPCI-824 FEP BLADE INTELLIGENT I/O CONTROLLER USER’S MANUAL The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Cyclone Microsystems, Inc. reserves the right to make changes to any products herein to improve reliability, function, or design. Cyclone Microsystems, Inc.
CONTENTS CHAPTER 1 1.1 INTRODUCTION ..............................................................................................................................1-1 1.2 FEATURES ......................................................................................................................................1-2 1.3 SPECIFICATIONS............................................................................................................................1-3 1.4 ENVIRONMENTAL........................
CONTENTS LIST OF FIGURES Figure 1-1. CPCI-824 Block Diagram ....................................................................................................1-1 Figure 1-2. CPCI-824 Physical Configuration ........................................................................................1-4 Figure 2-1. CPCI-824 Memory Map.......................................................................................................2-2 Figure 2-2. LED Register Bitmpa, E800 0001H ........................
CONTENTS LIST OF FIGURES Figure 1-1. CPCI-824 Block Diagram ....................................................................................................1-1 Figure 1-2. CPCI-824 Physical Configuration ........................................................................................1-4 Figure 2-1. CPCI-824 Memory Map.......................................................................................................2-2 Figure 2-2. LED Register Bitmpa, E800 0001H ........................
CHAPTER 1 GENERAL INTRODUCTION 1.1 INTRODUCTION The CompactPCI-824 is a Hot Swap Intelligent I/O Controller. The CPCI-824 card is based on the AMCC™ PowerPC™ 440GX, which is AMCC’s next generation integrated processor based on the PowerPCI 440 core operating at a frequency of 667 MHz. The 440GX supplies memory controller functions with up to 512 Mbytes of DDR SDRAM (64-bit with ECC) on an SoDIMM module at 333 MHz DDR.
GENERAL INTRODUCTION 1.2 • FEATURES PowerPC™ Processor • SDRAM Up to 512 MByte of 333 MHz DDR SDRAM is supported via a 200 pin SoDIMM module. • Flash ROM 8 Mbytes of in-circuit sector-programmable Flash ROM provides non-volatile storage on the CPCI-824. One 128 Kbyte sector of the Flash ROM is reserved for the storage of non-volatile boot and system parameters.
GENERAL INTRODUCTION 1.3 SPECIFICATIONS Physical Characteristics The CPCI-824 is a single slot, double high CompactPCI™ card with a peripheral slot interface. This product is equipped with an AMCC PowerPC 440GX mcroprocessor. Height Double Eurocard Depth Width Power Requirements 9.187” (233.35mm) (6U) 6.299” (160mm) .8” (20.32mm) The CPCI-824 requires +5V, +12V, -12V and +3.3V from the CompactPCI™ backplane J1 connector. The card is Universal and support either +3.3V or +5V V(I/O). Table 1-1.
GENERAL INTRODUCTION Figure 1-2. CPCI-824 Physical Configuration 1-4 CPCI-824 User’s Manual Revision 1.
GENERAL INTRODUCTION 1.5 REFERENCE MANUALS PowerPC 440GX Processor User’s Manual, Document# Data Sheet, Document # Applied Micro Circuits Corporation 6290 Sequence Drive San Diego, CA 92121 (800) 755-2622 http://www.amcc.com RC28F640J3 Strata Flash Data Sheet Developer’s Manual, Document #278848 Data Sheet, Document #278821 Intel Corporation Literature Sales P.O. Box 7641 16215 Alton Parkway Irvine, CA 92619-7013 http://www.broadcom.
GENERAL INTRODUCTION JTAG Debugger 1.6 Wind River HSI 500 Wind River Way Alameda, CA 94501 (510) 748-4100 http://www.windriver.com SOFTWARE DEVELOPMENT To simplify software development, Cyclone Microsystems has created the Breeze Development EnvironmentTM. Breeze includes initialization routines, hardware control routines and functions which provide a simple interface to the PCI bus.
HARDWARE CHAPTER 2 HARDWARE 2.1 AMCC POWERPC 440GX PROCESSOR The AMCC PowerPC 440GX Embedded Processor is a member of AMCC’s PowerPC 400 family of microprocessors. The 440GX on the CPCI-824 combines a powerful 667 MHz PowerPC core with intelligent peripherals and is designed to optimize I/O processing tasks. The 440GX processor consolidates into a single system: • AMCC PowerPC core. • 256 Kbyte L2 Cache. •32 Kbyte Data and Instruction Caches. •PCI-X interface.
HARDWARE 2.3 MEMORY MAP Figure 2-1 shows the CPCI-824 memory map, as configured by Breeze firmware.
HARDWARE Table 2-1. SDRAM Configurations DDR SDRAM Technology DDR SDRAM Arrangement # Banks Row Column Total Memory Size 128 Mbit 16M x 8 bit 1 12 10 128 Mbyte 2 12 10 256 Mbyte 1 12 9 64 Mbyte 2 12 9 128 Mbyte 1 13 10 256 Mbyte 2 13 10 512 Mbyte 1 13 9 128 Mbyte 2 13 9 256 Mbyte 1 13 11 512 Mbyte 2 13 11 1 Gbyte 1 13 10 256 Mbyte 2 13 10 512 Mbyte 8M x 16 bit 256 Mbit 32M x 8 bit 16M x 16 bit 512 Mbit 64M x 8 bit 32M x 16 bit 2.4.
HARDWARE Exceptions may be generated by the execution of instructions, or by signs from devices external to the PPCI440GX, the internal timer facilities, debug events, or error conditions. All interuupts, except for Machine Check, can be categorized according to two independent characteristics of the interrupt. They are asynchronous or synchronous and critical and non-critical. Asynchronous interrupts are caused by events that are independent of instruction execution.
HARDWARE Table 2-3. Console Serial Port Connector 2.7 Pin Signal Description 1 N/C Not Used 2 GND Signal Ground 3 TXD Transmit Data 4 RXD Receive Data 5 N/C Not Used 6 N/C Not Used ETHERNET The CPCI-824 has two 1 Gigabit Ethernet ports for CAT5 UTP (category 5 unshielded twisted pair). The CPCI-824 1 Gigabit Ethernet is based on the 10/100/1G Ethernet MAC contained in the 440GX and the Broadcom BCM5461 Gigabit Transciever (PHY). The interface between the MAC and PHY is RGMII.
HARDWARE 5 2.7.2 RX- Input TRD1- Input/Output 3 Not Used TR2+ Input/Output 2 Not Used TRD2- Input/Output 8 Not Used TRD3+ Input/Output 9 Not Used TRD3- Input/Output Gigabit Ethernet Port LEDs Both of the Gigabit Ethernet prots of the CPCI-824 have LEDs associated with the connector. The ports have the LEDs built into the RJ45 connectors. The “LNK” LED indicates, when lit, that the port is LINKed to a functional ethernet network.
HARDWARE 2.8 PERIPHERAL BUS The CPCI-824 utilizes the 440GX External Bus Controller (EBC) as a data communication path to the Flash memory and other peripheral devices such as LEDs and the CPLD for the external register control. The address/data path is on a programmable 8-bit width bus and operates at high bandwidth. 2.8.1 Flash ROM The CPCI-824 provides 8 Mbytes of sector-programmable Flash ROM for non-volatile code storage.
HARDWARE Table 2-6. Breeze Start-up LEDS LED TESTS ACT TLBs set. External bus controller set ST0 PCB arbitration priorities set ST1 Interrupt controller set IOP UART set ACT, ST0 System reset check done. ACT, ST1 I2C bus set. (first pass) ACT, IOP Board configuration initialized ST0, ST1 Board strapping validated ST0, IOP I2C bus set. (second pass) ST1, IP SDRAM initialized ACT, ST0, ST1 None 2.8.4 SDRAM checked and cleared.
HARDWARE 2.8.5 Power Supply Monitoring Two circuits are provided for monitoring the health of power supplies. Additional inputs to the CompactPCI connector define pins for degraded, failed and detected power supplies. The definitions for the CompactPCI connector J2 is provided in Appendix B. A failed or degraded power supply, as long as it is detected, will cause an interrupt to the processor. Additionally, the state of the power supply as defined by POWERGOOD, i.e.
HARDWARE Table 2-7. I2C Device Addresses 2.10.1 Designator Device Function Address J10 DDR SDRAM EEPROM SODIMM Memory Configuration 10100011 U13 LM75 Temperature Sensor 1001000x U1 LM75 Temperature Sensor 1001001x U16 24C08-LV Serial EEPROM 1010000x SDRAM EEPROM The EEPROM located on the DDR SDRAM module contains identification and configuration information. Breeze code will read this information on power-up and will properly configure the PPC440GX processor to the SDRAM type.
HARDWARE Table 2-8. JTAG Emulator Pin Assignment CPCI-824 User’s Manual Revision 1.
APPENDIX A PMC MODULE INTERFACE A.1 INTRODUCTION The PMC Module Interface allows PCI devices to be connected to the Local PCI interface of the CPCI824 host. The IEEE STD P1386.1, PCI Mezzanine Card (PMC), provides for one set of clocking and arbitration signals per PMC Module. Cyclone Microsystems has expanded this to two sets per PMC Module on the CPCI-824. With ability to connect a PMC module on the CPCI-824, up to two devices are supported.
PMC MODULE INTERFACE Table A-1. PMC Clock & Arbitration Assignment MODULE IDSEL ADDR IDSEL# CLOCK ARBITRATION PMC 0 IDSEL# AD17 J12.25 CLKA REQ0#,GNT0# PMC 0 IDSEL1# AD18 J12.34 CLKB REQ1#,GNT1# Table A-2. PMC Interrupt Assignment A.4 DEVICE INTx# 1ST DEVICE 2ND DEVICE INTA# INTA# INTB# INTB# INTB# INTC# INTC# INTC# INTD# INTD# INTD# INTA# PMC MODULE CONNECTOR PMC Modules use three board-to-board connectors (plug) with 64 pins each. The receptacles (i.e.
PMC MODULE INTERFACE Table A-3.
PMC MODULE INTERFACE Table A-4. P22 PMC Module Connector Pinout A-4 Pin Signal Pin Signal 1 +12V 2 TRST# 3 TMS 4 TDO 5 TDI 6 GND 7 GND 8 PCI-RSVD 9 PCI-RSVD 10 PCI-RSVD 11 BUSMODE2# 12 +3.3V 13 RST# 14 BUSMODE3# 15 +3.3V 16 BUSMODE4# 17 PCI-RSVD 18 GND 19 AD30 20 AD29 21 GND 22 AD26 23 AD24 24 +3.3V 25 IDSEL 26 AD23 27 +3.3V 28 AD20 29 AD18 30 GND 31 AD16 32 C/BE2# 33 GND 34 PMC+IDSEL1 35 TRDY# 36 +3.
PMC MODULE INTERFACE Table A-5.
APPENDIX B CPCI J2 DEFINITION B.1 INTRODUCTION The CPCI-824 utilizes some of the reserved pins in J2 for Fan and Power Supply status information. Differences from the CPCI specification are shown in table B-1. Pin Table B-1. CPCI-824 J2 Definition C D E 20 FAL1# GND DET0# 21 FAN1 FAN0 DET1# CPCI-824 User’s Manual Revision 1.
