User's Manual
Table Of Contents
- General Description
- Benefits
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Module Connections
- Bluetooth Baseband Core
- Infrared Modulator
- Infrared Learning
- Wireless Charging
- Security
- Support for NFC Tag Based Pairing
- Bluetooth Smart Audio
- ADC Port
- Serial Peripheral Interface
- Microprocessor Unit
- Integrated Radio Transceiver
- Peripheral Transport Unit
- GPIO Port
- PWM
- Power Management Unit
- Electrical Characteristics
- RF Specifications
- Timing and AC Characteristics
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
Document Number: 002-xxxxx Rev. ** Page 30 of 42
PRELIMINARY
CYBLE-013025-00
CYBLE-013030-00
Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
UART Timing
Figure 15. UART Timing
SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when 2.2V > VDDIO
≥ 1.62V.
Figure 16 and Figure 17 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively.
Table 21. UART Timing Specifications
Reference Characteristics Min Max Unit
1 Delay time, UART_CTS_N low to UART_TXD valid – 24 Baud out cycles
2 Setup time, UART_CTS_N high before midpoint of stop bit – 10 ns
3 Delay time, midpoint of stop bit to UART_RTS_N high – 2 Baud out cycles
Table 22. SPI Interface Timing Specifications
Reference Characteristics Min Typ Max
1 Time from CSN asserted to first clock edge 1 SCK 100 ?
2 Master setup time – ¾ SCK –
3 Master hold time ¾ SCK – –
4 Slave setup time – ¾ SCK –
5Slave hold time ¾ SCK––
6 Time from last clock edge to CSN deasserted 1 SCK 10 SCK 100