User's Manual

Document Number: 002-xxxxx Rev. ** Page 32 of 42
PRELIMINARY
CYBLE-013025-00
CYBLE-013030-00
Figure 18. BSC Interface Timing Diagram
7 Data input setup time 100 – ns
8 STOP condition setup time 280 – ns
9 Output valid from clock – 400 ns
10 Bus free time
2
650 – ns
1. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions.
2. Time that the cbus must be free before a new transaction can start.
Table 23. BSC Interface Timing Specifications
Reference Characteristics Min Max Unit