User's Manual
Table Of Contents
- General Description
- Benefits
- More Information
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Module Connections
- Connections and Optional External Components
- Bluetooth Baseband Core
- Microprocessor Unit
- Integrated Radio Transceiver
- Collaborative Coexistence
- Global Coexistence Interface
- Peripheral Transport Unit
- PCM Interface
- Clock Frequencies
- GPIO Port
- PWM
- Triac Control/PWM
- Serial Peripheral Interface
- Power Management Unit
- Electrical Characteristics
- RF Specifications
- Timing and AC Characteristics
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
Document Number: 002-19525 Rev. ** Page 20 of 49
PRELIMINARY
CYBT-343026-01
CYBT-343029-01
CYBT-143038-01
UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 6
Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI
command. The CYBT-X430XX-01 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The
interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps. The baud rate
of the CYBT-X430XX-01UART is controlled by two values. The first is aU ART clock divisor (set in the DLBR register) that divides the
UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a
number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first
half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time.
Tabl e 8 contains example values to generate common baud rates with a 24 MHz UART clock.
Tabl e 9 contains example values to generate common baud rates with a 48 MHz UART clock.
Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during
normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud
rate registers.
The CYBT-X430XX-01 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is
within ±2%
Table 8. Common Baud Rate Examples, 24 MHz Clock
Baud Rate (bps)
Baud Rate Adjustment
Mode Error (%)
High Nibble Low Nibble
3M 0xFF 0xF8 High rate 0.00
2M 0XFF 0XF4 High rate 0.00
1M 0X44 0XFF Normal 0.00
921600 0x05 0x05 Normal 0.16
460800 0x02 0x02 Normal 0.16
230400 0x04 0x04 Normal 0.16
115200 0x00 0x00 Normal 0.16
57600 0x00 0x00 Normal 0.16
38400 0x01 0x00 Normal 0.00
Table 9. Common Baud Rate Examples, 48 MHz Clock
Baud Rate (bps) High Rate Low Rate Mode Error (%)
6M 0xFF 0xF8 High rate 0
4M 0xFF 0xF4 High rate 0
3M 0x0 0xFF Normal 0
2M 0x44 0xFF Normal 0
1.5M 0x0 0xFE Normal 0
1M 0x0 0xFD Normal 0
921600 0x22 0xFD Normal 0.16
230400 0x0 0xF3 Normal 0.16
115200 0x1 0xE6 Normal –0.08
57600 0x1 0xCC Normal 0.04
38400 0x11 0xB2 Normal 0