User's Manual

Document Number: 002-19525 Rev. ** Page 21 of 49
PRELIMINARY
CYBT-343026-01
CYBT-343029-01
CYBT-143038-01
Peripheral UART Interface
The CYBT-X430XX-01 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed
through the optional I/O ports, which can be configured individually and separately for each functional pin as shown in Table 5 and
Tabl e 6.
PCM Interface
The CYBT-X430XX-01 includes a PCM interface that shares pins with the I
2
S interface. The PCM Interface on the CYBT-013033-01
can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-013033-01 generates the PCM_CLK
and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the
CYBT-X430XX-01.
Slot Mapping
The CYBT-X430XX-01 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample
interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or
1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM
data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow
other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM
clock during the last bit of the slot.
Frame Synchronization
The CYBT-X430XX-01 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchro-
nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and
is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.
Data Formatting
The CYBT-X430XX-01 may be configured to generate and accept several different data formats. For conventional narrowband speech
mode, the CYBT-X430XX-01 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to
support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a
sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
Burst PCM Mode
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and
save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with
an HCI command from the host.
Clock Frequencies
The CYBT-X430XX-01 has an integrated 24 MHz crystal on the module. There is no need to add an additional crystal oscillator.
Table 10. CYBT-X430XX-01 Peripheral UART
Pin Name pUART_TX pUART_RX pUART_CTS_N pUART_RTS_N
Configured pin name
P0 ( P2 P3 P6
P31P33–P30