User's Manual
Table Of Contents
- General Description
- Benefits
- More Information
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Module Connections
- Connections and Optional External Components
- Bluetooth Baseband Core
- Microprocessor Unit
- Integrated Radio Transceiver
- Collaborative Coexistence
- Global Coexistence Interface
- Peripheral Transport Unit
- PCM Interface
- Clock Frequencies
- GPIO Port
- PWM
- Triac Control/PWM
- Serial Peripheral Interface
- Power Management Unit
- Electrical Characteristics
- RF Specifications
- Timing and AC Characteristics
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
Document Number: 002-19525 Rev. ** Page 31 of 49
PRELIMINARY
CYBT-343026-01
CYBT-343029-01
CYBT-143038-01
SPI Timing
The SPI interface supports clock speeds up to 12 MHz
Tabl e 20 and Figure 13 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively.
Table 20. SPI Mode 0 and 2
Figure 13. SPI Timing – Mode 0 and 2
Tabl e 21 and Figure 14 show the timing requirements when operating in SPI Mode 1 and 3.
Reference Characteristics Minimum Maximum Unit
1
Time from slave assert SPI_INT to master assert SPI_CSN (Direc-
tRead)
0?ns
2
Time from master assert SPI_CSN to slave assert SPI_INT (Direct-
Write)
0?ns
3 Time from master assert SPI_CSN to first clock edge 20 ? ns
4 Setup time for MOSI data lines 8
<FmNumerator
>1
/<FmDeno
minator>2
SCK
ns
5 Hold time for MOSI data lines 8
<FmNumerator
>1
/<FmDeno
minator>2
SCK
ns
6 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100 ns
7 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 ? ns
8 Idle time between subsequent SPI transactions 1 SCK ? ns