User's Manual

Document Number: 002-19525 Rev. ** Page 37 of 49
PRELIMINARY
CYBT-343026-01
CYBT-343029-01
CYBT-143038-01
Long Frame Sync, Slave Mode
Figure 19. PCM Timing Diagram (Long Frame Sync, Slave Mode)
Table 26. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Reference Characteristics Minimum Typical Maximum Unit
1 PCM bit clock frequency – – TBD MHz
2 PCM bit clock LOW TBD – – ns
3 PCM bit clock HIGH TBD – – ns
4 PCM_SYNC setup TBD – – ns
5 PCM_SYNC hold TBD – – ns
6 PCM_OUT delay TBD – TBD ns
7 PCM_IN setup TBD – – ns
8 PCM_IN hold TBD – – ns
9
Delay from rising edge of PCM_BCLK during last bit period
to PCM_OUT becoming high impedance
TBD – TBD ns