User's Manual

Document Number: 002-19525 Rev. ** Page 38 of 49
PRELIMINARY
CYBT-343026-01
CYBT-343029-01
CYBT-143038-01
I
2
S Interface Timing
The I
2
S interface supports both master and slave modes. The I
2
S signals are:
n I
2
S clock: I
2
S SCK
n I
2
S Word Select: I
2
S WS
n I
2
S Data Out: I
2
S SDO
n I
2
S Data In: I
2
S SDI
I
2
S SCK and I
2
S WS become outputs in master mode and inputs in slave mode, while I
2
S SDO always stays as an output. The channel
word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I
2
S bus, per the
I
2
S specification. The MSB of each data word is transmitted one bit clock cycle after the I
2
S WS transition, synchronous with the falling
edge of bit clock. Left-channel data is transmitted when I
2
S WS is low, and right-channel data is transmitted when I
2
S WS is high.
Data bits sent by the CYBT-013033-01 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on
the rising edge of I2S_SSCK.
The clock rate in master mode is either of the following:
n 48 kHz x 32 bits per frame = 1.536 MHz
n 48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any clock rate is supported
to a maximum of 3.072 MHz. Timing values specified in Ta bl e 27 are relative to high and low threshold levels.
Table 27. Timing for I
2
S Transmitters and Receivers
Transmitter Receiver
Notes
Lower LImit Upper Limit Lower Limit Upper Limit
Min Max Min Max Min Max Min Max
Clock Period T
T
tr
–––
T
r
–––
1
1. The system clock period T must be greater than T
tr
and T
r
because both the transmitter and receiver have to be able to handle the data transfer rate.
Master Mode: Clock generated by transmitter or receiver
HIGH t
HC
0.35T
tr
–––
0.35T
tr
–––
2
2. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t
HC
and t
LC
are specified with
respect to T.
LOWt
LC
0.35T
tr
–––
0.35T
tr
–––
2
Slave Mode: Clock accepted by transmitter or receiver
HIGH t
HC
–
0.35T
tr
–––
0.35T
tr
––
3
3. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum
periods are greater than 0.35T
r
, any clock that meets the requirements can be used.
LOW t
LC
–
0.35T
tr
–––
0.35T
tr
––
3
Rise time t
RC
––
0.15T
tr
––– –
4
4. Because the delay (t
dtr
) and the maximum transmitter speed (defined by T
tr
) are related, a fast transmitter driven by a slow clock edge can result in t
dtr
not
exceeding t
RC
which means t
htr
becomes zero or negative. Therefore, the transmitter has to guarantee that t
htr
is greater than or equal to zero, so long as the
clock rise-time t
RC
is not more than t
RCmax
, where t
RCmax
is not less than 0.15T
tr
.
Transmitter
Delay t
dtr
–––0.8T––––
5
5. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient
setup time.
Hold time t
htr
0–––––––
5
Receiver
Setup time t
sr
–––––
0.2T
r
––
6
6. The data setup and hold time must not be less than the specified receiver setup and hold time.
Hold time t
hr
–––––0––
6