Specifications

Document Number: 002-26540 Rev. ** Page 17 of 45
PRELIMINARY
CYBT-213043-02
Microcontroller Unit
The CYBT-213043-02 includes a Cortex-M4 processor with 1 MB of program ROM, 160 KB of data RAM, 16 KB of patch RAM, and
256 KB of flash. The CM4 has a maximum speed of 96 MHz. The 256 KB of flash is supported by an 8 KB cache allowing direct code
execution from flash at near maximum speed and low power consumption.
The CM4 runs all the BT layers as well as application code. The ROM includes LMAC, HCI, L2CAP, GATT, as well as other stack
layers freeing up most of the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support.
External Reset
Figure 10 shows power on and reset timing of the CYBT-213043-02. After VBAT is applied and reset is inactive, the internal buck
turns on, followed by the RF and Digital LDOs. Once the LDO outputs have stabilized, the PMU allows the digital core to come out of
reset. As shown in the figure, external reset can be applied at any time subsequent to power up.
Figure 10. Reset Timing
32-kHz Crystal Oscillator
The CYBT-213043-02 includes connections for an external 32-kHz oscillator to provide accurate timing during low power operations.
Figure 11 shows the 32-kHz XTAL oscillator with external components and Table 9 lists the oscillator characteristics. This oscillator
can be operated with a 32 kHz or 32.768-kHz crystal oscillator or be driven with a clock input at similar frequency. The XTAL must
have an accuracy of ±250 ppm or better per the BT spec over temperature and including aging. The default component values are:
R1 = 10 MO and C1 = C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.
Figure 11. 32 kHz Oscillator Block Diagram