Specifications

Document Number: 002-26540 Rev. ** Page 24 of 45
PRELIMINARY
CYBT-213043-02
Current Consumption
Table 14 provides the current consumption measurements taken at the input of LDOIN and VDDIO combined (LDOIN = VDDIO =
3.0 V).
Silicon Core Buck Regulator
Table 14. Current Consumption
Operational Mode Conditions Typical Unit
HCI
48 MHz with Pause 1.3
mA
48 MHz without Pause 2.55
RX Continuous RX 5.9
TX Continuous TX - 4 dBm 5.8
PDS – 16.5
AePDS All RAM retained 8.7
HID-Off (SDS) 32 kHz XTAL on 1.75
Table 15. Core Buck Regulator
Parameter Conditions Min. Typ. Max. Unit
Input Supply, VBAT DC Range 1.62 3.0 3.63 V
Output Current
Active Mode – < 60 100
mA
PDS Mode – < 60 70
Output Voltage
Active Mode 1.1 1.26 1.4
V
PDS Mode, 40 mV min regulation window. 0.76
0.94 Avg
(0.92-0.96)
1.4
Output Voltage Accuracy
Active Mode, includes line and load regulation.
Before trim:
After trim:
–4
–2
–+4
+2
%
%
Ripple Voltage
Active Mode
2.2 H ± 25% inductor, DCR = 114 m ± 20%
4.7 F ± 10% capacitor, Total ESR < 20 m
–3–
mV
PDS Mode 40 40 –
Output Inductor, L
Components are included on module.
1.6
[3]
2.2 – H
Output Capacitor, C
OUT
3.0
[3]
4.7 –
F
Input Capacitor, C
IN
4.0
[3]
10 –
Input Supply Voltage Ramp
Time
0 to 3.3 V 40 – – s
Note
3. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.