Data Sheet
Table Of Contents
- CYBT-343052-02, EZ-BT WICED Module
- General Description
- Benefits
- More Information
- Contents
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Module Connections
- Connections and Optional External Components
- Functional Description
- Integrated Radio Transceiver
- Peripheral and Communication Interfaces
- Keyboard Scanner
- Clock Frequencies
- GPIO Port
- PWM
- Power Management Unit
- Electrical Characteristics
- Chipset RF Specifications
- Timing and AC Characteristics
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
Document Number: 002-28053 Rev. ** Page 21 of 47
CYBT-343052-02
Table 10 contains example values to generate common baud rates with a 48 MHz UART clock.
Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during
normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud
rate registers.
The CYBT-343052-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is
within ±2%.
Triac Control
The CYBT-343052-02 includes hardware support for zero-crossing detection and trigger control for up to four triacs. The
CYBT-343052-02 detects zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zero
crossing. This allows the CYBT-343052-02to be used in dimmer applications, as well as any other applications that require a control
signal that is offset from an input event.
The zero-crossing hardware includes an option to suppress glitches.
Peripheral UART Interface
The CYBT-343052-02 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through
the optional I/O ports, which can be configured individually and separately for each functional pin. The CYBT-343052-02 can map the
peripheral UART to any LHL GPIO. The peripheral UART clock is fixed at 24 MHz. Both TX and RX have a 256-byte FIFO (see Table
4 on page 9).
Serial Peripheral Interface
The CYBT-343052-02 has two independent SPI interfaces, both of which support single, dual, and quad mode SPI operations. Either
interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more
flexibility for user applications, the CYBT-343052-02 has optional I/O ports that can be configured individually and separately for each
functional pin. The CYBT-343052-02 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYBT-343052-02 can
also act as an SPI slave device that supports a 1.8V or 3.3V SPI master.
Note SPI voltage depends on VDDO/VDDM; therefore, it defines the type of devices that can be supported.
Table 10. Common Baud Rate Examples, 48 MHz Clock
Baud Rate (bps) High Rate Low Rate Mode Error (%)
6M 0xFF 0xF8 High rate 0
4M 0xFF 0xF4 High rate 0
3M 0x0 0xFF Normal 0
2M 0x44 0xFF Normal 0
1.5M 0x0 0xFE Normal 0
1M 0x0 0xFD Normal 0
921600 0x22 0xFD Normal 0.16
230400 0x0 0xF3 Normal 0.16
115200 0x1 0xE6 Normal –0.08
57600 0x1 0xCC Normal 0.04