Data Sheet
Table Of Contents
- CYBT-343052-02, EZ-BT WICED Module
- General Description
- Benefits
- More Information
- Contents
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Module Connections
- Connections and Optional External Components
- Functional Description
- Integrated Radio Transceiver
- Peripheral and Communication Interfaces
- Keyboard Scanner
- Clock Frequencies
- GPIO Port
- PWM
- Power Management Unit
- Electrical Characteristics
- Chipset RF Specifications
- Timing and AC Characteristics
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
Document Number: 002-28053 Rev. ** Page 32 of 47
CYBT-343052-02
Table 20 and Figure 15 show the timing requirements when operating in SPI Mode 1 and 3.
Figure 15. SPI Timing – Mode 1 and 3
Table 20. SPI Mode 1 and 3
Reference Characteristics Min Max Unit
1 Time from master assert SPI_CSN to first clock edge 45 –
ns
2 Hold time for MOSI data lines 12 ½ SCK
3 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100
4 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 –
5 Idle time between subsequent SPI transactions 1 SCK –
2
SPI_CSN
SPI_INT
(DirectWrite)
SPI_CLK
(Mode 1)
SPI_MOSI
Invalid bit
SPI_MISO
Not Driven
Invalid bit
First bit
First bit
Last bit
Last bit
1
3
4
5
Not Driven
SPI_CLK
(Mode 3)
SPI_INT
(DirectRead)