Specifications

Document Number: 002-28015 Rev. ** Page 28 of 42
PRELIMINARY
CYBT-243053-02
Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
UART Timing
Figure 13. UART Timing
SPI Timing
The SPI interface can be clocked up to 24 MHz.
Table 25 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2.
Table 24. UART Timing Specifications
Reference Characteristics Min Typ Max Unit
1 Delay time, UART_CTS_N low to UART_TXD valid. – – 1.50 Bit periods
2 Setup time, UART_CTS_N high before midpoint of stop bit. – – 0.67 Bit periods
3 Delay time, midpoint of stop bit to UART_RTS_N high. – – 1.33 Bit periods
Table 25. SPI Mode 0 and 2
Reference Characteristics Min Max Unit
1 Time from master assert SPI_CSN to first clock edge 45 – ns
2 Setup time for MOSI data lines 6 ¾
SCK ns
3 Idle time between subsequent SPI transactions 1 SCK – ns