Specifications

Document Number: 002-28015 Rev. ** Page 30 of 42
PRELIMINARY
CYBT-243053-02
I
2
C Compatible Interface Timing
The specifications in Table 26 references Figure .
Figure 16. I
2
C Interface Timing Diagram
Table 27. I2C Interface Timing Specifications (up to 1 MHz)
Reference Characteristics Min Max Unit
1 Clock frequency –
100 kHz
400 kHz
800 kHz
1000 kHz
2 START condition setup time 650 – ns
3 START condition hold time 280 – ns
4 Clock low time 650 – ns
5 Clock high time 280 – ns
6 Data input hold time
[13]
0 – ns
7 Data input setup time 100 – ns
8 STOP condition setup time 280 – ns
9 Output valid from clock – 400 ns
10 Bus free time
[14]
650 – ns
Notes
13. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
14. Time that the CBUS must be free before a new transaction can start.