Specifications

Document Number: 002-29172 Rev. ** Page 17 of 45
PRELIMINARY
CYBT-223058-02
CYBT-253059-02
Power Modes
The CYBT-2x305x-02 support the following HW power modes are supported:
■ Active mode - Normal operating mode in which all peripherals are available and the CPU is active.
■ Idle mode - CPU is paused.
■ Sleep mode - All system clocks are idle except for the LPO. The device can wake up either after a programmed period of time has
expired or if an external event is received via one of the GPIOs. In Sleep mode, the CPU is in WFI (wait for interrupt) and the HCLK
is not running. The PMU determines if the other clocks can be turned off and does accordingly. The state of the device is retained,
the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained.
■ Power Down Sleep (PDS) mode - Radio powered down and digital core mostly powered down except for RAM, registers, and
some core logic. CYBT-2x305x-02 can wake up either after a programmed period of time has expired or if an external event is
received via one of the GPIO.
■ Extended PDS (ePDS) - This is an extension of PDS Mode. In this mode, only the main RAM and ePDS control circuitry retains
power. As in other modes, the CYBT-2x305x-02 can wake up either after a programmed period or upon receiving an external event.
■ HID-OFF (Deep Sleep) mode - Core, radio, and regulators powered down. Only the GPIO domain is powered. In this mode, the
CYBT-2x305x-02 can be woken up either by an external event on one of the GPIOs or after a programmed period of time has
expired. The lowest power option for HID-Off mode is to wake by external event, allowing all clocking sources to remain off. If a
timed wake HID-Off state is desired, this is accomplished by powering the external or internal LPO. Current consumption will increase
slightly in timed wake HID-Off mode to account for the LPO power. After wakeup, the part will go through full FW initialization although
it will retain enough information to determine that it came out of HID-Off and the event that caused the wake up.
Transition between power modes is handled by the on-chip firmware with host/application involvement. In general, ePDS is the most
power-efficient mode for active use cases. HID-Off is preferable for non-connectable beacon use cases (long advertisement intervals).
Firmware
The CYBT-2x305x-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all
on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP, and SDP layers. The ROM also includes
drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power
modes. The ROM also supports OTA firmware update.
The CYBT-2x305x-02 is fully supported by the Cypress ModusToolbox IDE. ModusToolbox releases provide latest ROM patches,
drivers, and sample applications allowing customized applications using the CYBT-2x305x-02 to be built quickly and efficiently.
Watchdog
CYBT-2x305x-02 includes an onboard watchdog with a period of approximately 4 seconds. The watchdog generates an interrupt to
the Firmware after 2 seconds of inactivity and resets the device after 4 seconds.
Lockout Functionality
The CYBT-2x305x-02 powers up with SWD access to flash and RAM is disabled. After reset, FW checks OCF for the presence of a
security lockout field. If present, FW leaves SWD Flash and RAM access disabled and also blocks any HCI commands from reading
the raw contents of the RAM or Flash. This provides an effective way of protection against tampering, dumping, probing, or reverse
engineering of the user application stored in the on-chip flash. The only firmware upgrade path in this scenario is secure over-the-air
(OTA) update. The security field can be programmed in the factory after all programming and testing has been done.
True Random Number Generator
The CYBT-2x305x-02 includes a hardware TRNG (True Random Number Generator). Applications can access the random number
generator via firmware APIs.
Table 9. XTAL Oscillator Characteristics
Parameter Symbol Conditions Min Typ Max Unit
Output frequency F
oscout
– – 32.768 – kHz
Frequency tolerance – Over temperature and aging – – 250 ppm
XTAL drive level P
drv
For crystal selection – – 0.5 µW
XTAL series resistance R
series
For crystal selection – – 70 kΩ
XTAL shunt capacitance C
shunt
For crystal selection – – 2.2 pF
Load capacitance C
l
For crystal selection – 6 – pF