Specifications

Document Number: 002-29354 Rev. ** Page 12 of 45
PRELIMINARY
CYBT-273063-02
CYBT-263064-02
CYBT-263065-02
The design guidelines that should be followed when completing the Antenna Matching Network are as follows:
■ The AMN should be placed close to the antenna on the main board.
■ Routing to the AMN from the ANT pad on the module must be controlled to an impedance of 50 W.
The final AMN circuit may contain only a single component, or all three components shown above. The final number and type of
components will be determined based on the actual design of the system, and the final values for each component can be determined
through tuning the AMN. For details on how to properly tune an AMN, please refer to Application Note AN91445.
Figure 9 illustrates the CYBT-2X30XX-02 schematic.
Figure 9. CYBT-2X30XX-02 Schematic Diagram
5 4 3 2 1
Cypress Semiconductor Corp.
12
24
35
1
UART_TXD
UART_RTS_N
HOST_WAKE
UART_RXD
MODULE PAD ASSIGNMENT
GND
VDD
Castellated solder pad
1323
P4
XRES
GND
P2
UART_CTS_N
GND
(BOTTOM VIEW)
DEV_WAKE
P29
GND GND
P0
P1
P10
P13
P12
P11
P9
P14
P17
P5 P6
P26
P8
P15
XTALO_32K XTALI_32K
P37
P28
P3
Filter
Antenna Matching
P32
P27
TP37
ANT
37 External Antenna Pad
36 GND
TP36
CYBT-273063-02 PCB ANT
CYBT-263064-02
CYBT-263065-02
UFL CONN
EXTERNAL ANT PAD
BT_RF
P0
P1
P2
P3
P5
P6
P10
P12
P13
P15
P17
RXEN
XTALI_32K
UART_CTS_N
UART_RTS_N
UART_RXD
UART_TXD
HOST_WAKE
DEV_WAKE
XTALO_32K
XRES
P29
XRES
P26
P8
P28
TXEN
P9
P4
P11
P14
P29
P37
P9
P2
P17
XTALO_32K
XTALI_32K
P6
P5
P3
P13
P1
P0
P10
P12
P26
DEV_WAKE
HOST_WAKE
P15
P8
UART_RXD
UART_RTS_N
UART_CTS_N
UART_TXD
P37
P28
P11
P14
P4
BT_RF
RXEN
TXEN
DIGLDO_OUTVDD
RFLDO_OUT
DIGLDO_OUT
VDD
RFLDO_OUTCBUCK_OUT
RFLDO_OUT
VDD
VDD
Title
Size
Document Number Re v
Date: Sheet
of
630-20133-01
1.0
CYBT-273063_263064_263065-02
B
11Tuesday, August 20, 2019
Title
Size
Document Number Re v
Date: Sheet
of
630-20133-01
1.0
CYBT-273063_263064_263065-02
B
11Tuesday, August 20, 2019
Title
Size
Document Number Re v
Date: Sheet
of
630-20133-01
1.0
CYBT-273063_263064_263065-02
B
11Tuesday, August 20, 2019
LC8
0Ohm,0201
R1 10K,0201
C1512pF,0201
C10
2.2uF,0201
LC5 10pF,0201
12
LC1
TBD,0201
TP27
TP6
LC10
1.8pF,0201
C12
0.1uF,0201
LC2
0.9pF_TBD,0201
TP9
CYW20819_B62
U1B
PMU_LDO_ONLY_STRAP
E4
RFLDO_DIGLDO_VDDIN
E5
RF
H6
XTALO
E8
XTALI
F8
NC_0 (PALDO_VDDIN)
F5
IFVDD
F6
PMU_AVDD
G3
DIGLDO_VDDOUT
G4
NC_1 (PALDO_VDDOUT)
G5
PLLVDD
G8
SR_VLX
H2
SR_PVDD
H3
RFLDO_VDDOUT
H4
PAVDD
H5
VCOVDD
H8
XTALO_32K
A7
XTALI_32K
B7
PMU_AVSS
F4
PLLVSS
F7
PAVSS
G6
VCOVSS
G7
SR_PVSS
H1
IFVSS
H7
C14
10pF,0201
TP20
TP22
Y1
24MHz
LC4 10pF,0201
TP8
TP21
TP4
TP13
FB1 600@100M
TP30
TP2
C3
0.1uF,0201
TP1
TP11
R2 10K,0201
C1
0.1uF,0201
TP16
TP17
L1
2.2uH,0603
LC9
1.8pF,0201
TP25
TP3
LC11
2.7nH,0201
TP24
LC6 10pF,0201
C9
2.2uF,0201
TP26
TP15
TP29
TP35
C19
100pF,0201
TP19
C13
0.1uF,0201
LC3
5.6nH_TBD,0201
CYW20819_B62
U1A
ADC_AVSS
A8
UART_CTS_N
C7
UART_TXD
D6
UART_RXD
D7
HOST_WAKE
D8
UART_RTS_N
E6
DEV_WAKE
E7
RST_N
G1
JTAG_SEL
G2
P12
A1
P9
A2
P17
A3
P6
A4
P3
A5
P8
A6
P13
B1
P11
B2
P14
B3
P5
B4
P2
B5
P15
B6
P1
C1
P10
C2
P28
C4
P4
C5
P0
D2
P29
D3
P26
D4
P37
E2
P27
F1
P32
F2
VDDO1
B8
VDDC1
C8
VDDO2
D1
VDDC2
E1
VSSC1
C3
VSSC2
C6
VSSC3
E3
C17
1.0uF,0201
TP7
C1612pF,0201
C7
10uF,0402
FB2
600@100M
J1
UFL Connector_TE_1909763-1
1 2
3
TP31
8TR8201
U2
NC_1
1
GND_1
2
GND_2
3
TXRX
4
TXEN
5
RXEN
6
NC_2
7
GND_3
8
GND_4
9
ANT
10
GND_5
11
NC_3
12
DNC
13
VDD_1
14
NC_4
15
VDD_2
16
GND_6
17
TP18
C11
0.1uF,0201
TP5 TP28
TP12
TP33
TP32
TP23
TP34
C4
0.1uF,0201
TP14
LC7
DNI,0201
C2
0.1uF,0201
TP10
C8
4.7uF,0402