Specifications

Document Number: 002-29354 Rev. ** Page 19 of 45
PRELIMINARY
CYBT-273063-02
CYBT-263064-02
CYBT-263065-02
Peripherals and Communication Interfaces
I
2
C
The CYBT-2X30XX-02 provides a 2-pin I
2
C master/slave interface to communicate with I
2
C compatible peripherals. The following
transfer clock rates are supported:
■ 100 kHz
■ 400 kHz
■ 800 kHz (Not a standard I
2
C-compatible speed)
■ 1 MHz (Compatibility with high-speed I
2
C-compatible devices is not guaranteed)
The I
2
C compatible master is capable for doing read, write, write followed by read, and read followed by write operations where
read/write can be up to 64 bytes.
SCL and SDA lines can be routed to any of the configurable GPIOs (as indicated in Table 4), allowing for flexible system configuration.
When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I
2
C does not support
multimaster capability or flexible wait-state insertion by either master or slave devices.
HCI UART Interface
CYBT-2X30XX-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with
an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from
115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds are also
available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command.
The CYBT-2X30XX-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is
within ±5%. The UART interface CYBT-2X30XX-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced
data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
During HCI Mode, the DEV_WAKE signal can be programmed to wake up the CYBT-2X30XX-02 or allow the CYBT-2X30XX-02 to
sleep when radio activities permit. The CYBT-2X30XX-02 can also wake up the host as needed or allow the host to sleep via the
HOST_WAKE signal. Combined, the two signals allow the host and the CYBT-2X30XX-02 to optimize system power consumption by
allowing independent control of low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor-specific
command.
The FW UART driver allows applications to select different baud rates.
Peripheral UART Interface
The CYBT-2X30XX-02 has a second UART that may be used to interface to peripherals. Functionally, the peripheral UART is the
same as the HCI UART except for 256-byte TX/RX FIFOs. The peripheral UART is accessed through the I/O ports, which can be
configured individually and separately for each functional pin. The CYBT-2X30XX-02 can map the peripheral UART to any GPIO.
Serial Peripheral Interface
The CYBT-2X30XX-02 has two independent SPI interfaces. Both interfaces support single, dual, and Quad Mode SPI operations.
Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more
flexibility for user applications, the CYBT-2X30XX-02 has optional I/O ports that can be configured individually and separately for each
functional pin.
SPI IO voltage depends on VDDO.