Specifications

Table Of Contents
Document Number: 002-29354 Rev. ** Page 31 of 45
PRELIMINARY
CYBT-273063-02
CYBT-263064-02
CYBT-263065-02
SPI Timing
The SPI interface can be clocked up to 24 MHz.
Table 26 and Figure 15 show the timing requirements when operating in SPI Mode 0 and 2.
Figure 15. SPI Timing, Mode 0 and 2
Table 27 and Figure 16 show the timing requirements when operating in SPI Mode 1 and 3.
Table 26. SPI Mode 0 and 2
Reference Characteristics Min. Max. Unit
1 Time from master assert SPI_CSN to first clock edge 45
ns2 Setup time for MOSI data lines 6 ¾
SCK
3 Idle time between subsequent SPI transactions 1 SCK