Specifications

Document Number: 002-29354 Rev. ** Page 33 of 45
PRELIMINARY
CYBT-273063-02
CYBT-263064-02
CYBT-263065-02
I
2
C Compatible Interface Timing
The specifications in Table 27 references Figure .
Figure 17.
I
2
C Interface Timing Diagram
Table 28. I2C Interface Timing Specifications (up to 1 MHz)
Reference Characteristics Minimum Maximum Unit
1 Clock frequency –
100
kHz
400
800
1000
2 START condition setup time 650 –
ns
3 START condition hold time 280 –
4 Clock low time 650 –
5 Clock high time 280 –
6 Data input hold time
[13]
0 –
7 Data input setup time 100 –
8 STOP condition setup time 280 –
9 Output valid from clock – 400
10 Bus free time
[14]
650 –
Notes
13. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
14. Time that the CBUS must be free before a new transaction can start.