Data Sheet
Table Of Contents
- General description
- Module description
- Power consumption
- Functional capabilities
- Benefits
- More information
- References
- Development environments
- Technical support
- Contents
- 1 Overview
- 2 Pad connection interface
- 3 Recommended host PCB layout
- 4 Module connections
- 5 Connections and optional external components
- 6 Functional description
- 7 Integrated radio transceiver
- 8 Peripheral and communication interfaces
- 9 Keyboard scanner
- 10 Clock frequencies
- 11 GPIO port
- 12 PWM
- 13 Power management unit
- 14 Electrical characteristics
- 15 Chipset RF specifications
- 16 Timing and AC characteristics
- 17 Environmental specifications
- 18 Regulatory information
- 19 Packaging
- 20 Ordering information
- 21 Acronyms
- 22 Document conventions
- Revision History
Preliminary Datasheet 15 of 58 002-33419 Rev. **
2021-07-22
AIROC™ Bluetooth® LE module
Module connections
HOST_WAKE 36 BT_HOST_WAKE O VDDO Host wake-up. This is a signal from
the Bluetooth® device to the host
indicating that the Bluetooth®
device requires attention.
• Asserted: Host device must wake
up or remain awake
• Deasserted: Host device may
sleep when sleep awake criteria
is met. The polarity of this signal
is software configurable and can
be asserted high or low.
NA NA BT_RF I/O PAVDD2P5 RF antenna port
NA NA JTAG_SEL – – ARM JTAG debug mode control:
connect to GND for all applications
XRES 3 RST_N I VDDO Active-low system reset with
open-drain output and internal
pull-up resistor
Table 5 GPIO pin descriptions
Module
pad
name
Pad
number
Silicon
pin
name
Direction
Default
POR
state
Power
domain
Default alternate function description
P0 10 P0 Input Floating VDDO GPIO: P0
A/D converter input 29
Note Not available during TM1 = 1.
P1 9 P1 Input Floating VDDO GPIO: P1
A/D converter input 28
P2 34 P2 Input Floating VDDO GPIO: P2
P3 35 P3 Input Floating VDDO GPIO: P3
P4 37 P4 Input Floating VDDO GPIO: P4
P5 38 P5 Input Floating VDDO GPIO: P5
P6 39 P6 Input Floating VDDO GPIO: P6
P7 40 P7 Input Floating VDDO GPIO: P7
P8 41 P8 Input Floating VDDO GPIO: P8
A/D converter input 27
P9 17 P9 Input Floating VDDO GPIO: P9
A/D converter input 26
Table 4 Pin assignments
(continued)
Module pad
name
Pad
number
Silicon pin name I/O
Power
domain
Description
Notes
4. The CYBLE-3x307x-02 contains a single SPI (SPI1) peripheral supporting both master or slave configura-
tions. SPI2 is used for on-module serial memory interface.
5. In Master mode, any available GPIO can be configured as SPI1_CS. This function is not explicitly shown in
Table 20.