User's Manual

Table Of Contents
Document Number: 002-19043 Rev. PRELIMINARY Page 12 of 33
PRELIMINARY
CYBLE-413136-01
Microprocessor Unit
The CYBLE-413136-01 microprocessor unit runs software from the link control (LC) layer up to the host controller interface (HCI).
The microprocessor is a Cortex<Superscript>®-M4 32-bit RISC processor with embedded ICE-RT debug and serial wire debug
(SWD) interface units. The microprocessor also includes 2 MB of ROM memory for program storage and 512 KB of RAM for data
scratch-pad.
The internal ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At
power-up, the lower layer protocol stack is executed from the internal ROM.
External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. The device
also supports the integration of user applications and profiles. Patches and applications can be stored in on-chip flash.
Floating Point Unit
The CYBLE-413136-01 includes the CM4 single precision IEEE-754 compliant floating point unit. For additional details, see the Cor-
tex-M4 manual.
On-Chip Flash
The silicon device used in the CYBLE-413136-01 module includes 1 MB of on-chip flash. This flash can be used for direct program
execution or for non-volatile data. Typical usage for the on-chip flash includes:
n Chip configuration
n Patches
n Peer addresses and link keys
n Application code
n Application non-volatile data
n Product information
OTP
The CYBLE-413136-01 includes 2 KB of one-time programmable (OTP) memory. This memory can be used by the factory to store
product specific information.
Note: Use of OTP requires a 3 V supply to be present at all times.
External Reset
An external active-low reset signal, XRES, can be used to put the CYBLE-413136-01 in the reset state. An external voltage detector
reset IC with 50 ms delay is needed on the XRES. The XRES should be released only after the VDDO supply voltage level has been
stabilized for 50 ms.