User's Manual

Document Number: 002-19043 Rev. PRELIMINARY Page 14 of 33
PRELIMINARY
CYBLE-413136-01
Calibration
The CYBLE-413136-01 radio transceiver features a self-contained automated calibration scheme. No user interaction is required
during normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching net-
work, and amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process
and temperature variations into account, and it takes place transparently during normal operation and hop setting times.
Internal LDO Regulator
The CYBLE-413136-01 has an integrated 1.2 V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO reg-
ulator operates from a 1.425 V to 3.63 V input supply with a 30 mA maximum load current.
Peripheral Transport Unit
UART Interface
The CYBLE-413136-01 includes a UART interface for factory programming as well as when operating as a BT HCI device in a sys-
tem with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud
rates from 9600 bps to 6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a
vendor-specific UART HCI command. The CYBLE-413136-01 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to sup-
port enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2
kbaud.
The UART clock default setting is 24 MHz. The baud rate of the CYBLE-413136-01 UART is controlled by two values. The first is a
UART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate
adjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each
bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be
inserted into the end of each bit time. Table 6 contains example values to generate common baud rates with a 24 MHz UART clock.
Tab le 7 contains example values to generate common baud rates with a 48 MHz UART clock.
Table 6. Common Baud Rate Examples, 24 MHz Clock
Baud Rate (bps) DHBR DLBR Mode Error (%)
3M 0xFF 0xF8 High rate 0.00
2M 0XFF 0XF4 High rate 0.00
1.5M 0X00 0XFF Normal 0.00
1M 0x44 0xFF Normal 0.00
921600 0x55 0xFF Normal 0.16
460800 0x22 0xFD Normal 0.16
230400 0x44 0xFA Normal 0.16
115200 0x00 0xF3 Normal 0.16
38400 0x01 0xD9 Normal 0.00
Table 7. Common Baud Rate Examples, 48 MHz Clock
Baud Rate (bps) High Rate Low Rate Mode Error (%)
6M 0xFF 0xF8 High rate 0.00
4M 0xFF 0xF4 High rate 0.00
3M 0x0 0xFF Normal 0.00
2M 0x44 0xFF Normal 0.00
1.5M 0x00 0xFE Normal 0.00
1M 0x00 0xFD Normal 0.00
921600 0x22 0xFD Normal 0.16
460800 0x44 0xFA Normal 0.16