User's Manual

Document Number: 002-19043 Rev. PRELIMINARY Page 15 of 33
PRELIMINARY
CYBLE-413136-01
Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows
the host to adjust the contents of the baud rate registers.
The CYBLE-413136-01 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is
within ±5%.
Peripheral UART Interface
The CYBLE-413136-01 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through
the optional I/O ports, which can be configured individually and separately for each functional pin.
ADC Port
The ADC block is a single switched-cap Σ-Δ ADC core for audio and DC measurement. It operates at the 12 MHz clock rate. The
internal bandgap reference has ±5% accuracy without calibration. Different calibration and digital correction schemes can be applied
to reduce ADC absolute error and improve measurement accuracy in DC mode.
PWM
The CYBLE-413136-01 has four PWMs. The PWM module consists of the following:
n PWM1–4. Each of the four PWM channels contains the following registers:
p 16-bit initial value register (read/write)
p 16-bit toggle register (read/write)
p 16-bit PWM counter value register (read)
n PWM configuration register shared among PWM1–4 (read/write). This 18-bit register is used:
p To configure each PWM channel
p To select the clock of each PWM channel
p To change the phase of each PWM channel
Figure 10 shows the structure of one PWM.
230400 0x0 0xF3 Normal 0.16
115200 0x1 0xE6 Normal –0.08
57600 0x1 0xCC Normal 0.04
38400 0x11 0xB2 Normal 0.00
19200 0x22 0x64 Normal 0.00
Table 7. Common Baud Rate Examples, 48 MHz Clock (continued)
Baud Rate (bps) High Rate Low Rate Mode Error (%)