User's Manual

Document Number: 002-19043 Rev. PRELIMINARY Page 19 of 33
PRELIMINARY
CYBLE-413136-01
Digital LDO
Table 11. Digital LDO (Internal to Module)
Parameter Conditions Min. Typ. Max. Unit
Input supply voltage, Vin Minimum Vin=Vo+0.12V requirement must be met
under maximum load.
1.2 1.2 1.6 V
Nominal output voltage,Vo Internal default bit setting – 1.1 – V
Output voltage programmability Range
Step size
Accuracy at any step (including line/load regulation)
before trimming
Accuracy at any step (including line/load regulation)
after trimming
0.9
–
–4
–2
–
10
–
–
1.25
–
+4
+2
V
mV
%
%
Dropout voltage At maximum load – – 120 mV
Output current DC load
0.2
1
1. By default, an internal loading of ~0.2 mA resides inside the LDO. This is to ensure the LDO is stable with zero loading from the core. After the
core is up, digital logic can disable this internal loading by setting i_ldo_cntl<8:7> to 00.
–40mA
Output loading capacitor Internal, including the decoupling capacitor to be placed
next to the load and the equivalent loading capacitor by
the core.
4–10nF
Quiescent current At no load, excluding main bandgap Iq – 90 120
μA
Line regulation Vin from (Vo+0.12V) to 1.5V; 40 mA load – – 5 mV/V
Load regulation Load from 1 mA to 25 mA; Vin (Vo+0.12V) – 0.025 0.045 mV/mA
Leakage current In full power-down mode or bypass mode:
• Junction temperature: 25°C
• Junction temperature: 125°C
–
–
0.05
1.1
0.2
5.0
μA
μA
PSRR @1 kHz, Vin, Vo+0.12V
Output cap of 4 nF~10 nF
40 – – dB
PMU startup time VBAT is up and steady. Time from HID_OFF falling
edge to DIGLDO reaching 99% of Vo.
– 100 –
μs
LDO turn-on time LDO turn-on time when balance of chip is up – – 22
μs
External input capacitor Only use an external input capacitor at VDD_DIGLDO
pin if it is not supplied from CBUCK output.
–12.2
μF