User's Manual

Document Number: 002-19043 Rev. PRELIMINARY Page 20 of 33
PRELIMINARY
CYBLE-413136-01
RF LDO
Table 12. RF LDO (Internal to Module)
Parameter Conditions Min. Typ. Max. Unit
Input supply voltage, Vin Min Vin=Vo+0.15V = 1.35V (for Vo=1.2V)
Dropout voltage requirement must be met under
maximum load.
1.2 1.35 1.5 V
Nominal output voltage,Vo Internal default bit setting 000 – 1.2 – V
Output voltage programmability Range
Step size
Accuracy at any step (including line/load regulation)
Accuracy at any step (including line/load regulation)
after trimming
1.1
–
–4
–2
–
25
–
–
1.275
–
+4
+2
V
mV
%
%
Dropout voltage At maximum load – – 150 mV
Output current TBD 0.1 – 25 mA
Quiescent current No load – 44 –
μA
Line regulation Vin from (Vo+0.15V) to 1.5V; 25 mA load – – 5.5 mV/V
Load regulation
Load from 1 mA to 25 mA; Vin
≥ (Vo+0.15V)
– 0.025 0.045 mV/mA
Load step error
Load step from 1 mA–25 mA in 1
μs and
25 mA–1 mA in 1
μs; Vin(Vo+0.15V);
Co=2.2
μF
––35mV
Leakage current Power-down junction temperature: 85°C – – 10
μA
Output noise
@30 kHz, 25 mA load, Co= 2.2
μF
@100 kHz, 25 mA load, Co= 2.2
μF
––60
35
nV/
√Hz
nV/
√Hz
PSRR
@1kHz, Input > 1.35V, Co= 2.2
μF, Vo=1.2V
20 – – dB
LDO turn-on time LDO turn-on time when balance of chip is up – 140 180
μs
In-rush current
Vin=Vo+0.15V to 1.5V, Co=2.2
μF, no load
– – 100 mA
External output capacitor, Co Total ESR (trace/cap): 5 m–240 mW 0.5 2.2 4.7
μF
External input capacitor Only use an external input capacitor at VDD_DIGLDO
pin if it is not supplied from CBUCK output.
–12.2
μF
Note: Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and
aging.