User's Manual

PRELIMINARY
CYBLE-214009-00
Document Number: 002-09714 Rev. ** Page 16 of 40
Table 11. AC Specifications
GPIO
Parameter Description Min Typ Max Units Details/Conditions
F
CPU
CPU frequency DC – 48 MHz 1.71 V ≤ V
DD
≤ 5.5 V
T
SLEEP
Wakeup from Sleep mode – 0 – µs Guaranteed by characterization
T
DEEPSLEEP
Wakeup from Deep-Sleep mode – – 25 µs
24-MHz IMO. Guaranteed by
characterization
T
HIBERNATE
Wakeup from Hibernate mode – – 800 µs Guaranteed by characterization
T
STOP
Wakeup from Stop mode – – 2 ms XRES wakeup
Table 12. GPIO DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
V
IH
[4]
Input voltage HIGH threshold 0.7 × V
DD
– – V CMOS input
LVTTL input, V
DD
< 2.7 V 0.7 × V
DD
– – V –
LVTTL input, V
DD
≥ 2.7 V 2.0 – – V –
V
IL
Input voltage LOW threshold – – 0.3 × V
DD
VCMOS input
LVTTL input, V
DD
< 2.7 V – – 0.3× V
DD
V–
LVTTL input, V
DD
≥ 2.7 V – – 0.8 V –
V
OH
Output voltage HIGH level V
DD
–0.6 – – V I
OH
= 4 mA at 3.3-V V
DD
Output voltage HIGH level V
DD
–0.5 – – V I
OH
= 1 mA at 1.8-V V
DD
V
OL
Output voltage LOW level – – 0.6 V I
OL
= 8 mA at 3.3-V V
DD
Output voltage LOW level – – 0.6 V I
OL
= 4 mA at 1.8-V V
DD
Output voltage LOW level – – 0.4 V I
OL
= 3 mA at 3.3-V V
DD
R
PULLUP
Pull-up resistor 3.5 5.6 8.5 kΩ –
R
PULLDOWN
Pull-down resistor 3.5 5.6 8.5 kΩ –
I
IL
Input leakage current (absolute value) – – 2 nA 25 °C, V
DD
= 3.3 V
I
IL_CTBM
Input leakage on CTBm input pins – – 4 nA –
C
IN
Input capacitance – – 7 pF –
V
HYSTTL
Input hysteresis LVTTL 25 40 – mV V
DD
> 2.7 V
V
HYSCMOS
Input hysteresis CMOS 0.05 × V
DD
– – 1 –
I
DIODE
Current through protection diode to
V
DD
/V
SS
– – 100 µA –
I
TOT_GPIO
Maximum total source or sink chip
current
– – 200 mA –
Note
4. V
IH
must not exceed V
DD
+ 0.2 V.