User's Manual
Table Of Contents
- General Description
- Contents
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Power Supply Connections and Recommended External Components
- Electrical Specification
- Environmental Specifications
- Regulatory Information
- Ordering Information
- Acronyms
- Document Conventions
- Errata
- Document History Page
- Sales, Solutions, and Legal Information
PRELIMINARY
CYBLE-214009-00
Document Number: 002-09714 Rev. ** Page 23 of 40
Serial Communication
Table 30. Fixed I
2
C DC Specifications
Table 32. Fixed UART DC Specifications
Table 33. Fixed UART AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
I
I2C1
Block current consumption at 100 kHz – –
50
µA –
I
I2C2
Block current consumption at 400 kHz – –
155
µA –
I
I2C3
Block current consumption at 1 Mbps – –
390
µA –
I
I2C4
I
2
C enabled in Deep-Sleep mode – –
1.4
µA –
Table 31. Fixed I
2
C AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
F
I2C1
Bit rate – – 400 kHz
Parameter Description Min Typ Max Units Details/Conditions
I
UART1
Block current consumption at 100 kbps – – 55 µA –
I
UART2
Block current consumption at 1000 kbps – – 312 µA –
Parameter Description Min Typ Max Units Details/Conditions
F
UART
Bit rate – – 1 Mbps –
Table 34. Fixed SPI DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
I
SPI1
Block current consumption at 1 Mbps – – 360 µA –
I
SPI2
Block current consumption at 4 Mbps – – 560 µA –
I
SPI3
Block current consumption at 8 Mbps – – 600 µA –
Table 35. Fixed SPI AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
F
SPI
SPI operating frequency (master; 6x over sampling) – – 8 MHz –
Table 36. Fixed SPI Master Mode AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
T
DMO
MOSI valid after SCLK driving edge – – 18 ns –
T
DSI
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
20 – – ns Full clock, late MISO sampling
T
HMO
Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge
Table 37. Fixed SPI Slave Mode AC Specifications
Parameter Description Min Typ Max Units
T
DMI
MOSI valid before SCLK capturing edge 40 – – ns
T
DSO
MISO valid after SCLK driving edge – – 42 + 3 × T
CPU
ns
T
DSO_ext
MISO Valid after SCLK driving edge in
external clock mode. V
DD
< 3.0 V
– – 50 ns
T
HSO
Previous MISO data hold time 0 – – ns
T
SSELSCK
SSEL valid to first SCK valid edge 100 – – ns