User's Manual
Table Of Contents
- General Description
- Contents
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Power Supply Connections and Recommended External Components
- Electrical Specification
- Environmental Specifications
- Regulatory Information
- Ordering Information
- Acronyms
- Document Conventions
- Errata
- Document History Page
- Sales, Solutions, and Legal Information
PRELIMINARY
CYBLE-214009-00
Document Number: 002-09714 Rev. ** Page 26 of 40
Internal Main Oscillator
Internal Low-Speed Oscillator
Table 51. ECO Trim Value Specification
Table 47. IMO DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
I
IMO1
IMO operating current at 48 MHz – – 1000 µA –
I
IMO2
IMO operating current at 24 MHz – – 325 µA –
I
IMO3
IMO operating current at 12 MHz – – 225 µA –
I
IMO4
IMO operating current at 6 MHz – – 180 µA –
I
IMO5
IMO operating current at 3 MHz – – 150 µA –
Table 48. IMO AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
F
IMOTOL3
Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibration
F
IMOTOL3
IMO startup time – 12 – µs –
Table 49. ILO DC Specifications
Parameter Description Min Typ Max Units Details/Conditions
I
ILO2
ILO operating current at 32 kHz – 0.3 1.05 µA –
Table 50. ILO AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
T
STARTILO1
ILO startup time – – 2 ms –
F
ILOTRIM1
32-kHz trimmed frequency 15 32 50 kHz –
Parameter Description Value Details/Conditions
ECO
TRIM
24-MHz trim value
(firmware configuration)
0x00003FFA
Optimum trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
Table 52. UDB AC Specifications
Parameter Description Min Typ Max Units Details/Conditions
Data Path performance
F
MAX-TIMER
Max frequency of 16-bit timer in a UDB
pair
––48MHz
F
MAX-ADDER
Max frequency of 16-bit adder in a UDB
pair
––48MHz
F
MAX_CRC
Max frequency of 16-bit CRC/PRS in a
UDB pair
––48MHz
PLD Performance in UDB
F
MAX_PLD
Max frequency of 2-pass PLD function
in a UDB pair
––48MHz
Clock to Output Performance
T
CLK_OUT_UDB1
Prop. delay for clock in to data out at
25 °C, Typical
–15 – ns
T
CLK_OUT_UDB2
Prop. delay for clock in to data out,
Worst case
–25 – ns